mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 101

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

If a ColdFire processor encounters any type of fault during the exception processing of
another fault, the processor immediately halts execution with the catastrophic fault-on-fault
condition. A reset is required to force the processor to exit this halted state.
Debug
Interrupt
RTE and
Format Error
Exceptions
TRAP
Interrupt
Exception
Reset
Exception
Unsupported
Instruction
Exception
Exception
Caused by a hardware breakpoint register trigger. Rather than generating an IACK cycle, the
processor internally calculates the vector number (12 or 13, depending on the type of breakpoint
trigger). Additionally, the M bit and the interrupt priority mask fields of the SR are unaffected by the
interrupt. See Section 2.2.2.1, “Status Register (SR).”
The debug interrupt exception vector is expanded from Version 3 such that PC breakpoints are
distinguishable from other triggers. The two unique entries occur when a PC breakpoint generates
the 0x034 vector. In case of a two-level trigger, the last breakpoint event determines the vector.
The changes are described in more detail in Chapter 5, “Debug Support.”
When an RTE instruction executes, the processor first examines the 4-bit format field to validate the
frame type. For a ColdFire processor, any attempted execution of an RTE where the format is not
equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created
without disturbing the original exception frame and the stacked PC points to RTE.The selection of the
format value provides limited debug support for porting code from M68000 applications. On M68000
Family processors, the SR was at the top of the stack. Bit 30 of the longword addressed by the
system stack pointer is typically zero; so, attempting an RTE using this old format generates a format
error on a ColdFire processor.
If the format field defines a valid type, the processor does the following:
1 Reloads the SR operand.
2 Fetches the second longword operand.
3 Adjusts the stack pointer by adding the format value to the auto-incremented address after the first
4 Transfers control to the instruction address defined by the second longword operand in the stack
Executing TRAP always forces an exception and is useful for implementing system calls. The trap
instruction may be used to change from user to supervisor mode.
Interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized
and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt
vector. Autovectoring may optionally be configured through the system interface module (SIM). See
Section 9.2.2, “Autovector Register (AVR).”
Asserting the reset input signal (RSTI) causes a reset exception. Reset has the highest exception
priority; it provides for system initialization and recovery from catastrophic failure. When assertion of
RSTI is recognized, current processing is aborted and cannot be recovered. The reset exception
places the processor in supervisor mode by setting SR[S] and disables tracing by clearing SR[T].
This exception also clears SR[M] and sets the processor’s interrupt priority mask in the SR to the
highest level (level 7). Next, the VBR is initialized to 0x0000_0000. Configuration registers controlling
the operation of all processor-local memories are invalidated, disabling the memories.
Note: Other implementation-specific supervisor registers are also affected. Refer to each of the
modules in this manual for details on these registers.
After RSTI is negated, the processor waits 16 cycles before beginning the actual reset exception
process. During this time, certain events are sampled, including the assertion of the debug
breakpoint signal. If the processor is not halted, it initiates the reset exception by performing two
longword read bus cycles. The longword at address 0 is loaded into the stack pointer and the
longword at address 4 is loaded into the PC. After the initial instruction is fetched from memory,
program execution begins at the address in the PC. If an access error or address error occurs before
the first instruction executes, the processor enters the fault-on-fault halted state.
If the MCF5407 attempts to execute a valid instruction but the required optional hardware module is
not present in the OEP, a non-supported instruction exception is generated (vector 0x61). Control is
then passed to an exception handler that can then process the opcode as required by the system.
longword fetch.
frame.
Table 2-22. MCF5407 Exceptions (Continued)
Chapter 2. ColdFire Core
Description
Exception Processing Overview
2-35