mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 153

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Figure 4-14 shows the two possible states for a cache line in write-through mode.
Table 4-7 describes data cache line transitions and the accesses that cause them.
Read
miss
Read hit
Write
miss
(copy-
back)
Write
miss
(write-
through)
Write hit
(copy-
back)
Access
WI3—CPU write miss
WI5—DCINVA
WI6—CPUSHL & DDPI
WI7—CPUSHL & DDPI
(C,W)I1 Read line from
(C,W)I2 Not possible.
CI3
WI3
CI4
Figure 4-14. Data Cache Line State Diagram—Write-Through Mode
Invalid (V = 0)
memory and update
cache;
supply data to
processor;
go to valid state.
Read line from
memory and update
cache;
write data to cache;
go to modified state.
Write data to
memory;
stay in invalid state.
Not possible.
Table 4-7. Data Cache Line State Transitions
Invalid
V = 0
Chapter 4. Local Memory
(C,W)V1 Read new line from
(C,W)V2 Supply data to processor;
CV3
WV3
CV4
WI1—CPU read miss
WV5—DCINVA
WV6—CPUSHL & DDPI
Valid (V = 1, M = 0)
memory and update
cache;
supply data to processor;
stay in valid state.
stay in valid state.
Read new line from
memory and update
cache;
write data to cache;
go to modified state.
Write data to memory;
stay in valid state.
Write data to cache;
go to modified state.
Current State
V = 1
Valid
WD3 Write data to memory;
CD1 Push modified line to
CD2 Supply data to processor;
CD3 Push modified line to
CD4 Write data to cache;
Cache Operation Summary
Modified (V = 1, M = 1)
buffer;
read new line from memory
and update cache;
supply data to processor;
write push buffer contents
to memory;
go to valid state.
stay in modified state.
buffer;
read new line from memory
and update cache;
write push buffer contents
to memory;
stay in modified state.
stay in modified state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[DCINVA,ICINVA]
before switching modes.
stay in modified state.
WV1—CPU read miss
WV2—CPU read hit
WV3—CPU write miss
WV4—CPU write hit
WV7—CPUSHL & DDPI
4-29