mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 482
mcf5407
Manufacturer Part Number
mcf5407
Description
Mcf5407 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5407.pdf
(546 pages)
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Input/Output AC Timing Specifications
20.3 Input/Output AC Timing Specifications
Table 20-6 lists specifications for parameters shown in Figure 20-6 and Figure 20-7. Note
that inputs IRQ[7,5,3,1], BKPT, and AS are synchronized internally; that is, the logic level
is validated if the value does not change for two consecutive rising CLKIN edges. Setup
and hold times must be met only if recognition on a particular clock edge is required.
Table 20-7 lists specifications for timings in Figure 20-6, Figure 20-7, and Figure 20-13.
Although output signals that share a specification number have approximately the same
timing, due to loading differences, they do not necessarily change at the same time.
However, they have similar timings; that is, minimum and maximum times are not mixed.
20-6
B10
B11
B12
Num
1,2,3
3,4,5
6,7
1
2
3
Num
B1
B2
B3
B4
B5
B6
Inputs: BG, TA, A[23:0], PP[15:0], SIZ[1:0], R/W, TS, EDGESEL, D[31:0],
IRQ[7,5,3,1], and BKPT
Inputs: AS
Inputs: D[31:0]
PSTCLK
1
3
1
2
2
CLKIN rising to valid
CLKIN rising to invalid (hold)
CLKIN to high impedance (three-state)
Valid to CLKIN rising (setup)
CLKIN rising to invalid (hold)
Valid to CLKIN rising (setup)
CLKIN rising to invalid (hold)
CLKIN to input high impedance
CLKIN to EDGESEL delay
Table 20-7. Output AC Timing Specification
Table 20-6. Input AC Timing Specification
Characteristic
Characteristic
Figure 20-5. PSTCLK Timing
MCF5407 User’s Manual
C6
C5
0.5(C1) + 1.3
54 MHz CLKIN
1.0
Min
—
—
—
Min
7.5
1.0
—
C6
0
0
5
54 MHz CLKIN
Max
5.0
—
—
—
—
2
Max
10
8
10
—
Bus clock
4
5
Units
nS
nS
nS
nS
nS
Units
nS
nS
nS
nS
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