mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 155

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

In Table 4-10 the current state is modified.
Read miss
Read hit
Write miss
(copyback)
Write miss
(write-through)
Write hit
(copyback)
Write hit
(write-through)
Access
Table 4-10. Data Cache Line State Transitions (Current State Modified)
Read miss
Read hit
Write miss (copyback)
Write miss (write-through)
Write hit (copyback)
Write hit (write-through)
Cache invalidate
Cache push
Cache push
Table 4-9. Data Cache Line State Transitions (Current State Valid)
Access
WD3 Write data to memory;
WD4 Write data to memory and to cache;
CD1 Push modified line to buffer;
CD2 Supply data to processor;
CD3 Push modified line to buffer;
CD4 Write data to cache;
read new line from memory and update cache;
supply data to processor;
write push buffer contents to memory;
go to valid state.
stay in modified state.
read new line from memory and update cache;
write push buffer contents to memory;
stay in modified state.
stay in modified state.
Cache mode changed for the region corresponding to this line. To avoid this state,
execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
stay in modified state.
go to valid state.
Cache mode changed for the region corresponding to this line. To avoid this state,
execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
(C,W)V1 Read new line from memory and update cache;
(C,W)V2 Supply data to processor;
CV3
WV3
CV4
WV4
(C,W)V5 No action;
(C,W)V6 No action;
(C,W)V7 No action;
Chapter 4. Local Memory
supply data to processor; stay in valid state.
stay in valid state.
Read new line from memory and update cache;
write data to cache;
go to modified state.
Write data to memory;
stay in valid state.
Write data to cache;
go to modified state.
Write data to memory and to cache;
stay in valid state.
go to invalid state.
go to invalid state.
stay in valid state.
Response
Response
Cache Operation Summary
4-31