mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 363

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Reset
Field
Addr
R/W
14.3.19 UART Output Port Data Registers (UOP1n/UOP0n)
In UART mode, the RTS output can be asserted by writing a 1 to UOP1n[RTS] and negated
by writing a 1 to UOP0n[RTS]. UOP registers have no effect in modem mode. See
Figure 14-23.
Table 14-17 describes UOP1 fields.
14.4 UART Module Signal Definitions
Figure 14-24 shows both the external and internal signal groups.
Figure 14-24. UART Block Diagram Showing External and Internal Interface Signals
7–1
0
Bits
To Interrupt
Controller
Interface
—
RTS
to CPU
Name
External Clock (TIN)
(SIM)
7
Figure 14-23. UART Output Port Data 1 Register (UOP1/UOP0)
CLKIN
Reserved, should be cleared.
Output port parallel output. Controls assertion (UOP1)/negation (UOP0) of RTS output.
0 Not affected.
1 Asserts RTS (UOP1). Negates RTS (UOP0).
UART0: MBAR + 0x1F8 (UOP1), 0x1FC (UOP0); UART1 0x238 (UOP1), 0x23C (UOP0)
or
Address Bus
Control
Table 14-17. UOP1/UOP0 Field Descriptions
Data
IRQ
Internal
Control
Chapter 14. UART Modules
Logic
—
UART Module
Internal Bus
0000_0000
Write only
Description
Four-Character
Transmit Buffer
Receive Buffer
Two-Character
Clock Source
Output Port
Generator
Input Port
UART Module Signal Definitions
CTS
RTS
RxD
TxD
1
External
Interface
Signals
RTS
14-21
0