mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 48
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mcf5407
Manufacturer Part Number
mcf5407
Description
Mcf5407 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5407.pdf
(546 pages)
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MCF5407 Features
1.2 MCF5407 Features
The following list summarizes MCF5407 features:
1-4
• ColdFire processor core
• Multiply and accumulate unit (MAC)
• Hardware integer divide unit
• 16-Kbyte instruction cache, 8-Kbyte data cache
— Variable-length RISC, clock-multiplied Version 4 microprocessor core
— Implementation of Revision B of the ColdFire instruction set architecture (ISA),
— Two independent decoupled pipelines: four-stage instruction fetch pipeline (IFP)
— Ten-instruction FIFO buffer provides decoupling between the pipelines
— Limited superscalar design achieves performance levels close to dual-issue
— Programmable two-level branch acceleration mechanism with an 8-entry branch
— 32-bit internal address bus supporting 4 Gbytes of linear address space
— 32-bit data bus
— 16 user-accessible, 32-bit-wide, general-purpose registers
— Supervisor/user modes for system protection
— Vector base register to relocate exception-vector table
— Optimized for high-level language constructs
— High-speed, complex arithmetic processing for DSP applications
— Tightly coupled to the OEP
— Three-stage execute pipeline with one clock issue rate for 16 x 16 operations
— 16 x 16 and 32 x 32 multiplies support, all with 32-bit accumulate
— Signed or unsigned integer support, plus signed fractional operands
— Unsigned and signed integer divide support
— Tightly coupled to the OEP
— 32/16 and 32/32 operation support producing quotient and/or remainder results
— Four-way set-associative organization
— Operates at higher processor core frequency
— Provides pipelined, single-cycle access to critical code and data
— Data cache supports write-through and copyback modes
— Four-entry, 32-bit store buffer to improve performance of operand writes
which leverages the 68K programming model
and five-stage operand execution pipeline (OEP)
performance
cache plus a 128-entry prediction table for increased performance
MCF5407 User’s Manual
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