mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 60

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Status register (SR)
Vector base register
(VBR)
Cache configuration
register (CACR)
Access control
registers (ACR0/1,
ACR2/3)
RAM base address
registers (RAMBAR0,
RAMBAR1)
Module base address
register (MBAR)
Programming Model, Addressing Modes, and Instruction Set
1.4.3 Supervisor Registers
Table 1-2 summarizes the MCF5407 supervisor-level registers.
1.4.4 Instruction Set
The Version 4 ColdFire core implements Revision B of the instruction set, which adds
opcodes to enhance support for byte- and word-sized operands and position-independent
code. The ColdFire instruction set supports high-level languages and is optimized for those
instructions most commonly generated by compilers in embedded applications. Table 2-8
provides an alphabetized listing of the ColdFire instruction set opcodes, supported
Program counter
(PC)
Condition code
register (CCR)
MAC status
register (MACSR)
Accumulator
(ACC)
Mask register
(MASK)
1-16
Register
Register
Contains the address of the instruction currently being executed by the MCF5407 processor
The CCR is the lower byte of the SR. It contains indicator flags that reflect the result of a previous
operation and are used for conditional instruction execution.
Defines the operating configuration of the MAC unit and contains indicator flags from the results
of MAC instructions.
General-purpose register used to accumulate the results of MAC operations
General-purpose register provides an optional address mask for MAC instructions that fetch
operands from memory. It is useful in the implementation of circular queues in operand memory.
The upper byte of the SR provides interrupt information in addition to a variety of mode indicators
signaling the operating state of the ColdFire processor. The lower byte of the SR is the CCR, as
shown in Figure 1-4.
Defines the upper 12 bits of the base address of the exception vector table used during exception
processing. The low-order 20 bits are forced to zero, locating the vector table on 0-modulo-1
Mbyte address.
Defines the operating modes of the Version 4 cache memories. Control fields configuring the
instruction, data, and branch cache are provided by this register, along with the default attributes
for the 4-Gbyte address space.
Define address ranges and attributes associated with various memory regions within the 4-Gbyte
address space. Each ACR defines the location of a given memory region and assigns attributes
such as write-protection and cache mode (copyback, write-through, cacheability). ACR0 and
ACR1 support data memory; ACR2 and ACR3 support instruction memory. Additionally, CACR
fields assign default attributes to the instruction and data memory spaces.
Provide the logical base address for the two 2-Kbyte SRAM modules and define attributes and
access types allowed for the corresponding SRAM.
Defines the logical base address for the memory-mapped space containing the control registers
for the on-chip peripherals.
Table 1-1. User-Level Registers (Continued)
Table 1-2. Supervisor-Level Registers
MCF5407 User’s Manual
Description
Description