mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 451

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Table 18-8 defines the cycles for Figure 18-24.
Figure 18-25 shows a burst line access for an external master transfer with the chip select
set to no-wait states and with internal transfer-acknowledge assertion enabled.
C2–C3 The MCF5407 decodes the external master’s address and control signals to identify the proper chip select
Cycle
C10
C11
C1
C4
C5
C6
C7
C8
C9
The external master asserts HOLDREQ, signaling the MCF5407 to hold bus requests. BD should not be
asserted. The external master drives address, TS, R/W, TT[1:0], TM[2:0], TIP, and SIZ[1:0] as MCF5407
inputs.
and byte enable assertion. The external master negates TS in C2.
On the falling edge of CLKIN, the MCF5407 asserts the appropriate chip select for the external master
access along with the appropriate byte enables.
On the rising edge of CLKIN, data is driven onto the bus by the device selected by CS. On the rising edge,
the MCF5407 asserts TA to indicate the cycle is complete.
TA negates on the rising edge of CLKIN. On the falling edge, the MCF5407 negates the chip select and
byte enables and the next cycle can begin.
The external master negates TIP on the rising edge of CLKIN.
The external device retains bus mastership and drives the address bus, TS, R/W, TT[1:0], TM[2:0], TIP, and
SIZ[1:0] as inputs to the MCF5407.
The MCF5407 decodes the external master’s address and control signals to identify the proper chip select
and byte enable assertion. The external master negates TS. The MCF5407 asserts BR on the rising edge of
CLKIN, signalling that it wants to arbitrate for the bus when the current cycle completes.
The MCF5407 continues to decode the external device’s address and control signals to identify the proper
chip select and byte enable assertion.
On the falling edge of CLKIN, the MCF5407 asserts the appropriate chip select for the external master
access along with the appropriate byte enables.
Table 18-8. Cycles for Basic No-Wait-State External Master Access
Bus timing diagrams for external master transfers are not valid
for on-chip internal four-channel DMA accesses on the
MCF5407.
Timing diagrams describe transactions in general terms of bus
cycles (Cn) rather than the states (Sn) used in the bus diagrams.
Chapter 18. Bus Operation
NOTE:
Definition
General Operation of External Master Transfers
18-23