mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 414

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MCF5407 Bus Signals
17.2.2 Data Bus (D[31:0])
The data bus is bidirectional and non-multiplexed. Data is sampled by the MCF5407 on the
rising CLKIN edge. The data bus port width, wait states, and internal termination are
initially defined for the boot chip select by D[7:0] during reset. The port width for each chip
select and DRAM bank are programmable. The data bus uses a default configuration if none
of the chip selects or DRAM bank match the address decode. The default configuration is
a 32-bit port with external termination and burst-inhibited transfers. The data bus can
transfer byte, word, or longword data widths. All 32 data bus signals are driven during
writes, regardless of port width and operand size.
D[7:0] are used during reset initialization as inputs to configure the functions as described
in Table 17-3. They are defined in Section 17.5.5, “Data/Configuration Pins (D[7:0]).”
17.2.3 Read/Write (R/W)
When the MCF5407 is the bus master, it drives the R/W signal to indicate the direction of
subsequent data transfers. It is driven high during read bus cycles and driven low during
write bus cycles. This signal is an input during an external master access.
17.2.4 Size (SIZ[1:0])
When it is the bus master, the MCF5407 outputs these signals to indicate the requested data
transfer size. Table 17-4 shows the definition of the bus request size encodings. When the
MCF5407 device is not the bus master, these signals function as inputs.
Note that for misaligned transfers, SIZ[1:0] indicate the size of each transfer. For example,
17-8
D[6:5] Port size configuration (PS_CONFIG[1:0])
D[2:0] Divide control (DIVIDE[2:0])
Pin
D7
D4
D3
• A[31:24]—Pins are configured as address bits by setting corresponding PAR bits;
• PP[15:8]—Pins are configured as parallel port signals by clearing corresponding
they represent the most-significant address bus bits. As much as 4 Gbytes of
memory are available when all of these pins are programmed as address signals.
PAR bits; these represent the most-significant parallel port bits.
Auto-acknowledge configuration
(AA_CONFIG)
Address configuration (ADDR_CONFIG/D4) Section 17.5.6, “D4—Address Configuration
Byte enable configuration (BE_CONFIG)
Function
Table 17-3. Data Pin Configuration
MCF5407 User’s Manual
Section 17.5.5.2, “D7—Auto Acknowledge Configuration
(AA_CONFIG)”
Section 17.5.5.3, “D[6:5]—Port Size Configuration
(PS_CONFIG[1:0])”
(ADDR_CONFIG)”
Section 17.5.5.4, “D3—Byte-Enable Configuration
(BE_CONFIG)”
Section 17.5.6.1, “D[2:0]—Divide Control (DIVIDE[2:0])”
Section