mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 57

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

To support program trace, the Version 4 debug module has combined the processor status
and debug data outputs into a single 8-bit bus (PSTDDATA[7:0]). This bus and the
PSTCLK output provide execution status, captured operand data, and branch target
addresses defining processor activity at one-half the CPU’s clock rate.
1.3.10 PLL Module
The MCF5407 PLL module is shown in Figure 1-3.
The PLL module’s three modes of operation are described as follows.
1.4 Programming Model, Addressing Modes, and
The ColdFire programming model has two privilege levels—supervisor and user. The S bit
in the status register (SR) indicates the privilege level. The processor identifies a logical
address that differentiates between supervisor and user modes by accessing either the
supervisor or user address space.
• Reset mode—When RSTI is asserted, the PLL enters reset mode. At reset, the PLL
• Normal mode—In normal mode, the input frequency programmed at reset is
• Reduced-power mode—In reduced-power mode, the PCLK is disabled by executing
asserts RSTO from the MCF5407. The core:bus frequency ratio and other MCF5407
configuration information are sampled during reset.
clock-multiplied to provide the processor clock (PCLK).
a sequence that includes programming a control bit in the system configuration
register (SCR) and then executing the STOP instruction. Register contents are
retained in reduced-power mode, so the system can be reenabled quickly when an
unmasked interrupt or reset is detected.
Instruction Set
DIVIDE[2:0]
CLKIN
RSTI
Figure 1-3. PLL Module
PLL
Programming Model, Addressing Modes, and Instruction Set
Chapter 1. Overview
CLKIN (to on-chip peripherals)
BCLKO
PCLK (to core)
RSTO
PSTCLK (= PCLK/2)
Debug Module
÷2
1-13