mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 82

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Instruction Set Summary
2-16
<ea>y,<ea>x
Instruction
PSTDDATA
# <vector>
MACSR
#<data>
<label>
<shift>
<size>
MASK
Dy,Dx
Ry,Rx
Ay,Ax
<list>
<ea>
CCR
ACC
Rm
Rw
PC
SR
An
Dn
Rc
Rn
<>
cc
bc
dc
Xi
ic
Logical condition (example: NE for not equal)
Any address register n (example: A3 is address register 3)
Source and destination address registers, respectively
Any data register n (example: D5 is data register 5)
Source and destination data registers, respectively
Any control register (example VBR is the vector base register)
MAC registers (ACC, MAC, MASK)
Any address or data register
Destination register w (used for MAC instructions only)
Any source and destination registers, respectively
index register i (can be an address or data register: Ai, Di)
MAC accumulator register
Condition code register (lower byte of SR)
MAC status register
MAC mask register
Program counter
Status register
Processor status/debug data port
Immediate data following the 16-bit operation word of the instruction
Effective address
Source and destination effective addresses, respectively
Assembly language program label
List of registers for MOVEM instruction (example: D3–D0)
Shift operation: shift left (<<), shift right (>>)
Operand data size: byte (B), word (W), longword (L)
Both instruction and data caches
Data cache
Instruction cache
Identifies the 4-bit vector number for trap instructions
identifies an indirect data address referencing memory
Table 2-6. Notational Conventions
MCF5407 User’s Manual
Miscellaneous Operands
Register Specifications
Opcode Wildcard
Register Names
Port Name
Operand Syntax