mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 538

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

E
Electrical specifications
Exception processing
Execution timings
F
Features
H
Harvard memory architecture, 2-6
I
I
Index-2
2
C
signals, 17-16
synchronous operation, 11-16
cautions, 20-3
clock timing, 20-4
debug AC timing, 20-16
DMA timing, 20-23
general parameters, 20-1
I
input/output AC timing specifications, 20-6
JTAG AC timing, 20-24
parallel port timing, 20-22
reset timing, 20-15
timer module AC timing, 20-17
UART module AC timing, 20-19
overview, 2-31
processor exceptions, 2-34
stack frame definition, 2-32
miscellaneous, 2-29
one operand, 2-26
two operands, 2-27
process, 1-7
summary, 1-4
2
C input/output timing, 20-18
address and control, 11-5
mask, 11-7
address and control registers, 11-20
address multiplexing, 11-23
auto-refresh, 11-31
burst page mode, 11-27
continuous page mode, 11-29
controller signals, synchronous mode, 11-17
edge select, 11-18
general guidelines, 11-23
initialization, 11-32
interfacing, 11-27
mask registers, 11-22
mode register settings, 11-33
register set, 11-19
self-refresh, 11-32
MCF5407 User’s Manual
INDEX
IEEE Standard 1149.1 Test Access Port, see JTAG
Instruction execution times, 2-29
Instruction set
Integer data formats, 2-13
Integer data formats in memory, 2-14
Integer data formats in registers, 2-13
Interrupt controller
J
JTAG
address register, 8-6
arbitration procedure, 8-4
clock stretching, 8-5
clock synchronization, 8-5
control register, 8-7
data I/O register, 8-9
features, 8-1
frequency divider register, 8-6
handshaking, 8-5
interface memory map, B-8
lost arbitration, 8-13
overview, 8-1
programming examples, 8-10
programming model, 8-6
protocol, 8-3
repeated START generation, 8-12
slave mode, 8-13
software response, 8-11
START generation, 8-10
status register, 8-8
STOP generation, 8-12
system configuration, 8-3
timing specifications, 20-18
architecture additions, 2-18
architecture enhancements, 2-36
branch acceleration, 2-4
fetch pipeline, 2-4
MAC summary, 3-4
MAC unit execution times, 3-5
summary, 2-15, 2-19
autovector register, 9-5
overview, 9-1
pending and mask registers, 9-6
port assignment register, 9-7
AC timing, 20-24
obtaining IEEE Standard 1149.1, 19-11
overview, 19-1
registers
restrictions, 19-10
boundary scan, 19-7
bypass, 19-10
descriptions, 19-4
IDCODE, 19-6
instruction shift, 19-5