mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 127

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Accesses are attempted in the following order:
4.4 SRAM Programming Model
The SRAM programming model consists of RAMBAR0 and RAMBAR1.
4.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1)
The SRAM modules are configured through the RAMBARs, shown in Figure 4-1.
Address
RAMBARn fields are described in detail in Table 4-1.
31–11 BA
10–9
8
7
Reset
Bits
Field
R/W
1. SRAM
2. Cache (if space is defined as cacheable)
3. External access
• Each RAMBAR holds the base address of the SRAM. The MOVEC instruction
• Each RAMBAR can be read or written from the debug module in a similar manner.
• All undefined RAMBAR bits are reserved. These bits are ignored during writes to
• The valid bits, RAMBARn[V], are cleared at reset, disabling the SRAM modules.
provides write-only access to this register from the processor.
the RAMBAR and return zeros when read from the debug module.
All other bits are unaffected.
—
WP
D/I
31
Name
Base address. Defines the SRAM module’s word-aligned base address. Each SRAM module
occupies a 2-Kbyte space defined by the contents of BA. SRAM may reside on any 2-Kbyte
boundary in the 4-Gbyte address space.
Reserved, should be cleared.
Write protect. Controls read/write properties of the SRAM.
0 Allows read and write accesses to the SRAM module
1 Allows only read accesses to the SRAM module. Any attempted write reference generates an
Data/instruction bus. Indicates whether SRAM is connected to the internal data or instruction bus.
0 Data bus
1 Instruction bus
Figure 4-1. SRAM Base Address Registers (RAMBARn)
access error exception to the ColdFire processor core.
CPU space + 0xC04 (RAMBAR0), CPU space + 0xC05 (RAMBAR1)
Table 4-1. RAMBARn Field Description
BA
Chapter 4. Local Memory
W for CPU; R/W for debug
—
Description
11
10
—
9
WP D/I — C/I SC SD UC UD
8
7
SRAM Programming Model
6
5
4
3
2
1
4-3
V
0
0