mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 429

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Chapter 18
Bus Operation
This chapter describes data-transfer operations, error conditions, bus arbitration, and reset
operations. It describes transfers initiated by the MCF5407 and by an external bus master,
and includes detailed timing diagrams showing the interaction of signals in supported bus
operations. Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,”
describes DRAM cycles.
18.1 Features
The following list summarizes bus operation features:
Note that, throughout this manual, an overbar indicates an active-low signal.
18.2 Bus and Control Signals
Table 18-1 summarizes MCF5407 bus signals described in Chapter 17, “Signal
Descriptions.”
Signal Name
• Up to 32 bits of address and data
• 8-, 16-, and 32-bit port sizes
• Byte, word, longword, and line size transfers
• Bus arbitration for external devices
• Burst and burst-inhibited transfer support
• Internal termination for core and DMA bus cycles
• External termination of bus cycles controlled by an external bus master
BE/BWE
CS[7:0]
A[31:0]
D[31:0]
AS
1
1
Address strobe
Address bus
Byte enable/Byte write enable
Chip selects
Data bus
Table 18-1. ColdFire Bus Signal Summary
Description
Chapter 18. Bus Operation
O
O
O
O
I/O
MCF5407 Master
I
I
O
O
I/O
External Master
Falling
Rising
Falling
Falling
Rising
Edge
18-1