mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 172

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Programming Model
Table 5-12 describes DBRn fields.
Table 5-13 describes DBMRn fields.
DBRs support both aligned and misaligned references. Table 5-14 shows relationships
between processor address, access size, and location within the 32-bit data bus.
5.4.6 Program Counter Breakpoint/Mask Registers
Each PC breakpoint register (PBR, PBR1, PBR2, PBR3) defines an instruction address for
use as part of the trigger. These registers’ contents are compared with the processor’s
DRc[4–0]
5-16
31–0
31–0
Bits
Bits
Reset
Figure 5-10. Data Breakpoint/Mask Registers (DBR/DBR1 and DBMR/DBMR1)
Field
R/W DBR and DBR1 are accessible in supervisor mode as debug control register 0x0E and 0x1E, using the
Mask
Data
Name
Name
WDEBUG instruction and through the BDM port using the
DBMR and DBMR1 are accessible in supervisor mode as debug control register 0x0F and 0x0F1 using the
WDEBUG instruction and via the BDM port using the
(PBR, PBR1, PBR2, PBR3, PBMR)
31
Data breakpoint value. Contains the value to be compared with the data value from the processor’s
local bus as a breakpoint trigger.
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBRn bit allows
the corresponding DBRn bit to be compared to the appropriate bit of the processor’s local data bus.
Setting a DBMRn bit causes that bit to be ignored.
Table 5-14. Access Size and Operand Data Location
Table 5-13. DBMRn Field Descriptions
Table 5-12. DBRn Field Descriptions
A[1:0]
0x0E (DBR), 0x1E (DBR1); 0x0F (DBMR), 0x1F (DBMR1)
00
01
10
11
0x
1x
xx
Data (DBR/DBR1); Mask (DBMR/DBMR1)
MCF5407 User’s Manual
Access Size
Longword
Word
Word
Byte
Byte
Byte
Byte
Uninitialized
Description
Description
WDMREG
RDMREG
Operand Location
command.
D[31:24]
D[23:16]
D[31:16]
D[15:8]
D[15:0]
D[31:0]
D[7:0]
and
WDMREG
commands.
0