mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 135

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

4.9 Cache Operation
Figure 4-5 shows the general flow of a caching operation using the 8-Kbyte data cache as
an example. The discussion in this chapter assumes a data cache. Instruction cache
operations are similar except that there is no support for writing to the cache; therefore such
notions of modified cache lines and write allocation do not apply.
The following steps determine if a data cache line is allocated for a given address:
31
1. The cache set index, A[10:4], selects one cache set.
2. A[31:11] and the cache set index are used as a tag reference or are used to update
3. The four tags from the selected cache set are compared with the tag reference. A
Tag Data/Tag Reference
the cache line tag field. Note that A[31:11] can specify 21 possible addresses that
can be mapped to one of the four ways.
cache hit occurs if a tag matches the tag reference and the V bit is set, indicating that
the cache line contains valid data. If a cacheable write access hits in a valid cache
line, the write can occur to the cache line without having to load it from memory.
If the memory space is copyback, the updated cache line is marked modified
(M = 1), because the new data has made the data in memory out of date. If the
memory location is write-through, the write is passed on to system memory and the
M bit is never used. Note that the tag does not have TT or TM bits.
Address
A[31:11]
Address
Select
A[10:4]
Set
Figure 4-5. Data Caching Operation
11
10
Chapter 4. Local Memory
Index
Set 0
Set 1
Set 127
•
•
•
Comparator
4
3
TAG
TAG
0
•
•
•
STATUS LW0 LW1 LW2 LW3
STATUS LW0 LW1 LW2 LW3
0
•
•
•
1
Way 0
2
Way 1
•
•
•
3
Way 2
•
•
•
Hit 3
Hit 2
Hit 1
Hit 0
Way 3
•
•
•
•
•
•
Logical OR
MUX
Cache Operation
Line Select
Data
Hit
4-11