mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 21

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

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Figure
Number
MCF5407 Block Diagram............................................................................................. 1-2
UART Module Block Diagram................................................................................... 1-10
PLL Module ................................................................................................................ 1-13
ColdFire MCF5407 Programming Model .................................................................. 1-15
ColdFire Enhanced Pipeline ......................................................................................... 2-3
ColdFire Multiply-Accumulate Functionality Diagram ............................................... 2-5
ColdFire Programming Model...................................................................................... 2-8
Condition Code Register (CCR) ................................................................................... 2-9
Status Register (SR).................................................................................................... 2-11
Vector Base Register (VBR)....................................................................................... 2-12
Organization of Integer Data Formats in Data Registers............................................ 2-13
Organization of Integer Data Formats in Address Registers ...................................... 2-14
Memory Operand Addressing..................................................................................... 2-14
Exception Stack Frame Form...................................................................................... 2-33
ColdFire MAC Multiplication and Accumulation........................................................ 3-2
MAC Programming Model ........................................................................................... 3-2
SRAM Base Address Registers (RAMBARn) ............................................................. 4-3
Data Cache Organization .............................................................................................. 4-7
Data Cache Organization and Line Format .................................................................. 4-8
Data Cache—A: at Reset, B: after Invalidation, C and D: Loading Pattern............... 4-10
Data Caching Operation.............................................................................................. 4-11
Write-Miss in Copyback Mode................................................................................... 4-16
Data Cache Locking.................................................................................................... 4-20
Cache Control Register (CACR) ................................................................................ 4-21
Access Control Register Format (ACRn) ................................................................... 4-24
An Format (Data Cache)............................................................................................. 4-25
An Format (Instruction Cache) ................................................................................... 4-25
Instruction Cache Line State Diagram........................................................................ 4-27
Data Cache Line State Diagram—Copyback Mode ................................................... 4-28
Data Cache Line State Diagram—Write-Through Mode ........................................... 4-29
Processor/Debug Module Interface............................................................................... 5-1
PSTCLK Timing........................................................................................................... 5-3
PSTDDATA: Single-Cycle Instruction Timing............................................................ 5-3
Example JMP Instruction Output on PSTDDATA....................................................... 5-6
Debug Programming Model ......................................................................................... 5-9
Address Attribute Trigger Registers (AATR, AATR1).............................................. 5-11
ILLUSTRATIONS
Illustrations
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