mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 375

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

14.5.2.6 FIFOs in UART1
For UART1, FIFOs can be accessed as longwords. Other properties are as follows:
The Tx FIFO functions as follows:
The Rx FIFO functions as follows:
• 8-bit CODEC mode (MODCTL[MODE] = 01):
• For two-sample accesses, the samples occupy internal data bus bits 31–16.16-bit
• AC ‘97 mode (MODCTL[MODE] = 11):
• AC ‘97 mode—Tx FIFO is effectively a 16 x 20 dual-port RAM to hold sixteen
• For all other modes the Tx FIFO is effectively 8 x 32.
• AC ‘97 mode—Rx FIFO is effectively a 16 x 21 dual-port RAM to hold sixteen
— Can access FIFOs either one, two, or four 1-byte samples at a time.
— For one-sample accesses, the sample occupies internal data bus bits 31–24.
CODEC mode (MODCTL[MODE] = 10):
— Can access FIFOs one or two 2-byte samples at a time.
— For one-sample accesses, the sample occupies internal data bus bits 31–16.
— Must access FIFOs one sample at a time
— Because time slot 1 has 16 bits, compared to 20 for all other time slots in a frame,
— All 20-bit time slots occupy internal data bus bits 31–12 for Tx and Rx FIFOs.
— In addition, when the Rx FIFO is being read, a 1 in internal data bus bit 11 marks
20-bit AC ‘97 time slots. One sample/time slot is written to Tx FIFO per internal bus
cycle.
— 8-bit CODEC or as a UART—Tx FIFO can hold thirty-two 8-bit samples. One,
— 16-bit CODEC—Tx FIFO can hold sixteen 16-bit samples. Either one or two
20-bit AC ‘97 time slots. The extra flag bit is set to indicate the first time slot of a
new AC ‘97 frame. One sample/time slot is read from Rx FIFO per internal bus
cycle.
time slot 1 data occupies internal data bus bits 31–16.
this sample as the first time slot of a new frame.
two, or four bytes/samples can be written to Tx FIFO per internal bus cycle.
16-bit samples can be written to Tx FIFO per internal bus cycle.
The receiver can still read characters in the FIFO stack if the
receiver is disabled. If the receiver is reset, the FIFO stack, RTS
control, all receiver status bits, and interrupt requests are reset.
No more characters are received until the receiver is reenabled.
Chapter 14. UART Modules
NOTE:
Operation
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