mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 84

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Instruction Set Summary
2.6.1 Additions to the Instruction Set Architecture
The original ColdFire instruction set architecture (ISA) was derived from the M68000
Family opcodes based on extensive analysis of embedded application code. After the initial
ColdFire compilers were created, developers identified ISA additions that would enhance
both code density and overall performance. Additionally, as users implemented
ColdFire-based designs into a wide range of embedded systems, they identified frequently
used instruction sequences that could be improved by the creation of new instructions. This
observation was especially prevalent in development environments that made use of
substantial amounts of assembly language code.
The original ISA definition minimized the support for instructions referencing byte and
word operands. Full support for the MOVE.B and MOVEC.W instructions was provided,
but clr (clear) and tst (test) are the only other opcodes supporting these data types. Based
on input from compiler writers and system users, a set of instruction enhancements was
proposed that address the two following areas:
The following list summarizes new and enhanced instructions of Revision_B ISA:
2-18
Instruction
• Enhanced support for byte and word-sized operands through new move operations
• Enhanced support for position-independent code
• New instructions:
C
N
V
X
Z
— INTOUCH loads blocks of instructions to be locked in the instruction cache
— MOV3Q.L moves 3-bit immediate data to the destination location
— MVS.{B,W} sign-extends the source operand and moves it to the destination
— MVZ.{B,W} zero-fills the source operand and moves it to the destination
— SATS.L updates the destination register depending on CCR[V] and bit 31 of the
— TAS.B performs an indivisible read-modify-write cycle to test and set the
register
register
register
addressed memory byte.
Carry
Negative
Overflow
Extend
Zero
Table 2-6. Notational Conventions (Continued)
Condition Code Register Bit Names
MCF5407 User’s Manual
Operand Syntax