mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 140

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Cache Operation
4.9.3.1 Read Miss
A processor read that misses in the cache requests the cache controller to generate a bus
transaction. This bus transaction reads the needed line from memory and supplies the
required data to the processor core. The line is placed in the cache in the valid state.
4.9.3.2 Write Miss (Data Cache Only)
The cache controller handles processor writes that miss in the data cache differently for
write-through and copyback regions. Write misses to copyback regions cause the cache line
to be read from system memory, as shown in Figure 4-6.
The new cache line is then updated with write data and the M bit is set for the line, leaving
it in modified state. Write misses to write-through regions write directly to memory without
loading the corresponding cache line into the cache.
4.9.3.3 Read Hit
On a read hit, the cache provides the data to the processor core and the cache line state
remains unchanged. If the cache mode changes for a specific region of address space, lines
in the cache corresponding to that region that contain modified data are not pushed out to
memory when a read hit occurs within that line. First execute a CPUSHL instruction or set
CACR[DCINVA,ICINVA] before switching the cache mode.
1. Writing character X to 0x0B generates a write miss. Data cannot be written to an invalid line.
4-16
3. After the cache line is filled, the write that initiated the write miss (the character X) completes to 0x0B.
2. The cache line (characters A–P) is updated from system memory, and line is marked valid.
MCF5407
MCF5407
Figure 4-6. Write-Miss in Copyback Mode
X
ABCD EFGH IJKL MNOP
ABCD EXGH IJKL MNOP
0x0C
0x0C
0x0C
MCF5407 User’s Manual
0x08 0x04
0x08 0x04
0x08 0x04
Cache Line
0x00
0x00
0x00
M = 0
V = 0
M = 0
V = 1
M = 1
V = 1
Memory
System