mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 219

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Table 6-2 describes MBAR fields.
The following example shows how to set the MBAR to location 0x1000_0000 using the D0
register. Setting MBAR[V] validates the MBAR location. This example assumes all
accesses are valid:
move.1 #0x10000001,DO
movec DO,MBAR
6.2.3 Reset Status Register (RSR)
The reset status register (RSR), Figure 6-3, contains two status bits, HRST and SWTR.
Reset control logic sets one of the bits depending on whether the last reset was caused by
an external device asserting RSTI (HRST = 1) or by the software watchdog timer
(SWTR = 1). Only one RSR bit can be set at any time. If a reset occurs, reset control logic
sets only the bit that indicates the cause of reset.
31–12
11–9
Bits
8
7
6
5
4
3
2
1
0
Field
WP
AM
SC
SD
UC
UD
BA
C/I
—
—
V
Base address. Defines the base address for a 4-Kbyte address range.
Reserved, should be cleared.
Write protect. Mask bit for write cycles in the MBAR-mapped register address range.
0 Module address range is read/write.
1 Module address range is read only.
Reserved, should be cleared.
Alternate master mask. When AM = 0 and an alternate master (external master or DMA) accesses
MBAR-mapped registers, MBAR[SC,SD,UC,UD] are ignored in address decoding. These fields
mask address space, placing the MBAR-mapped register in a specific address space or spaces.
Mask CPU space and interrupt acknowledge cycles.
0 Activates the corresponding MBAR-mapped register
1 Regular external bus access
Setting masks supervisor code space in MBAR address range
Setting masks supervisor data space in MBAR address range
Setting masks user code space in MBAR address range
Setting masks user data space in MBAR address range
Valid. Determines whether MBAR settings are valid.
0 MBAR contents are invalid.
1 MBAR contents are valid.
Address
Reset
Field HRST
R/W
1/0
Figure 6-3. Reset Status Register (RSR)
7
Table 6-2. MBAR Field Descriptions
—
0
6
Chapter 6. SIM Overview
SWTR
1/0
5
MBAR + 0x000
Read/Write
4
Description
0_0000
—
Programming Model
0
6-5