upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 839

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

JR
LD.B
LD.BU
LD.H
LDSR
LD.HU
LD.W
MOV
MOVEA
MOVHI
MUL
MULH
MULHI
MULU
NOP
NOT
NOT1
OR
ORI
PREPARE
Mnemonic
(2/4)
disp22
disp16[reg1],reg2
disp16[reg1],reg2
disp16[reg1],reg2
reg2,regID
disp16[reg1],reg2
disp16[reg1],reg2
reg1,reg2
imm5,reg2
imm32,reg1
imm16,reg1,reg2
imm16,reg1,reg2
reg1,reg2,reg3
imm9,reg2,reg3
reg1,reg2
imm5,reg2
imm16,reg1,reg2
reg1,reg2,reg3
imm9,reg2,reg3
reg1,reg2
bit#3,disp16[reg1]
reg2,[reg1]
reg1,reg2
imm16,reg1,reg2
list12,imm5
list12,imm5,
sp/imm
Operand
Note 15
Note 7
Notes 8, 10
Note 8
Note 12
Note 8
Note 8
imm16/imm32
Note 16
0000011110dddddd
ddddddddddddddd0
rrrrr111000RRRRR
dddddddddddddddd
rrrrr11110bRRRRR
rrrrr111001RRRRR
ddddddddddddddd0
rrrrr111111RRRRR
0000000000100000
rrrrr111111RRRRR
ddddddddddddddd1
rrrrr111001RRRRR
ddddddddddddddd1
rrrrr000000RRRRR GR[reg2]←GR[reg1]
rrrrr010000iiiii GR[reg2]←sign-extend(imm5)
00000110001RRRRR
iiiiiiiiiiiiiiii
iiiiiiiiiiiiiiii
rrrrr110001RRRRR
iiiiiiiiiiiiiiii
rrrrr110010RRRRR
iiiiiiiiiiiiiiii GR[reg2]←GR[reg1] + (imm16 ll 0
rrrrr111111RRRRR
wwwww01000100000
rrrrr111111iiiii
wwwww01001IIII00
rrrrr000111RRRRR GR[reg2]←GR[reg2]
rrrrr010111iiiii GR[reg2]←GR[reg2]
rrrrr110111RRRRR
iiiiiiiiiiiiiiii GR[reg2]←GR[reg1]
rrrrr111111RRRRR
wwwww01000100010
rrrrr111111iiiii
wwwww01001IIII10
0000000000000000 Pass at least one clock cycle doing nothing.
rrrrr000001RRRRR GR[reg2]←NOT(GR[reg1])
01bbb111110RRRRR
dddddddddddddddd
rrrrr111111RRRRR
0000000011100010
rrrrr001000RRRRR GR[reg2]←GR[reg2]OR GR[reg1]
rrrrr110100RRRRR
iiiiiiiiiiiiiiii
0000011110iiiiiL
LLLLLLLLLLL00001
0000011110iiiiiL
LLLLLLLLLLLff011
dddddddddddddd1
Opcode
User’s Manual U16702EE3V2UD00
Appendix A
PC←PC + sign-extend(disp22)
adr←GR[reg1] + sign-extend(disp16)
GR[reg2]←sign-extend(Load-memory(adr,Byte))
adr←GR[reg1] + sign-extend(disp16)
GR[reg2]←zero-extend(Load-memory(adr,Byte))
adr←GR[reg1] + sign-extend(disp16)
GR[reg2]←sign-extend(Load-memory(adr,Half-word))
SR[regID]←GR[reg2]
adr←GR[reg1]+sign-exend(disp16)
GR[reg2]←zero-extend(Load-memory(adr,half-word)
adr←GR[reg1] + sign-exend(disp16)
GR[reg2]←Load-memory(adr,Word)
GR[reg1]←imm32
GR[reg2]←GR[reg1] + sign-extend(imm16)
GR[reg3] ll GR[reg2]←GR[reg2] × GR[reg1]
GR[reg3] ll GR[reg2]←GR[reg2] × sign-extend(imm9)
Note 13
GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
GR[reg3] ll GR[reg2]←GR[reg2]xzero-extend(imm9)
Note 13
adr←GR[reg1]+sign-extend(disp16)
Z flag←Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,Z flag)
adr←GR[reg1]
Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,Z flag)
GR[reg2]←GR[reg1]OR zero-extend(imm16)
Store-memory(sp – 4,GR[reg in list12],Word)
sp←sp – 4
repeat 1 step above until all regs in list12 are stored
sp←sp – zero-extend(imm5)
Store-memory(sp – 4,GR[reg in list12],Word)
sp←sp – 4
repeat 1 step above until all regs in list12 are stored
sp←sp – zero-extend(imm5)
ep←sp/imm
Instruction Set List
Note 6
Note 6
Note 6
Operation
× GR[reg1]
× sign-extend(imm5)
× imm16
16
)
Note 6
Other than
regID = PSW
regID = PSW
Note
Note
Note
Note
Note
n+1
n+2
17
2
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
3
3
3
3
1
1
4
4
Execution
i
Clock
Note
Note
Note
Note
Note
Note
Note
Note
Note
n+1
n+2
14
14
14
14
17
2
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
r
2
2
2
2
3
3
3
3
4
4
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
n+1
n+2
11
11
11
11
17
2
1
1
1
1
2
1
1
2
2
2
2
2
2
2
1
1
1
1
9
3
3
3
3
4
4
l
CY OV S
×
×
0
0
0
Flags
×
×
×
×
Z SAT
×
×
×
×
×
×
839
×