upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 410

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

UAnCTL2 UAnBRS7 UAnBRS6 UAnBRS5 UAnBRS4 UAnBRS3 UAnBRS2 UAnBRS1 UAnBRS0
(3)
Remark:
UAnBRS7 UAnBRS6 UAnBRS5 UAnBRS4 UAnBRS3 UAnBRS2 UAnBRS1 UAnBRS0
Remark:
Cautions: 1. This register can be rewritten only when the UAnPWR bit of the UAnCTL0 register
For details on the baud rate generator, please refer to section 12.6 ”Dedicated Baud Rate Genera-
tor” on page 425.
410
Symbol
0
0
0
0
1
1
1
1
:
UARTAn control register 2 (UAnCTL2)
The UAnCTL2 register is used to select the baud rate (serial transfer rate) clock of UARTAn.
This register can be read or written in 8-bit units.
Reset input sets this register to FFH.
Address: UA0CTL2: FFFFFA02H, UA1CTL2: FFFFFA12H
n = 0 to 1
f
2. The baud rate is the serial clock divided by two.
XCLK
7
0
0
0
0
1
1
1
1
:
= 0 or when the UAnTXE bit = UAnRXE bit = 0.
is the frequency of the base clock selected by the UAnCTL1 register.
Figure 12-4: UARTAn Control Register 2 (UAnCTL2) Format
Chapter 12 Asynchronous Serial Interface A (UARTA)
6
0
0
0
0
1
1
0
1
:
5
0
0
0
0
1
1
1
1
:
User’s Manual U16702EE3V2UD00
4
0
0
0
0
1
1
1
1
:
3
0
1
1
1
1
1
1
1
:
2
–
0
0
1
0
0
1
1
:
1
–
0
1
0
0
1
0
1
:
value (k)
Rated
0
252
253
254
255
–
4
5
6
:
Address R/W
Setting prohibited
Serial clock
f
f
f
f
XCLK
XCLK
XCLK
XCLK
f
f
f
XCLK
XCLK
XCLK
R/W FFH
:
/252
/253
/254
/255
/4
/5
/6
Reset
After