upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 483

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

14.3.8 Description of the FIFO Buffer Transfer Mode
When the TRMD bit in the CSIM register is set “1”, the Queued CSI operates in FIFO buffer transfer
mode.
Transfer start condition in FIFO buffer transfer mode:
The transmission data number must be set in SFN[3:0]. Note that writing a value greater than 16 to the
SFN register is prohibited, as the FIFO buffer design can hold up to 16 elements only.
The transfer starts by copying the first data element - pointed to by SIO Load/Store FIFO pointer - to the
SIO shift register. At that time the transmission status flag CSOT is set to “1”, and the CS3n[3:0] pins
output the CS value from the FIFO.
When the transfer of the data element is finished, the received data overwrites the location in the FIFO
using the SIO Load/Store FIFO pointer, and the SIO Load/Store FIFO pointer is then incremented.
[CTXE = 1 or CRXE = 1] and
[Data exists in FIFO (SFEMP = 0)]
CS3n3 to CS3n0 pins
SFCS register
3, 2, 1, 0
19
CS
3, 2, 1, 0
CS data 4
CS data 3
CS data 2
CS data 1
CS data 0
SFCS
Figure 14-19: FIFO Buffer Transfer Mode Data Handling
16
15, 14, 13, ......
15
Chapter 14 Queued CSI (CSI30, CSI31)
Data
SO3n
User’s Manual U16702EE3V2UD00
15, 14, 13, ......2, 1, 0
Transmission data 3
Transmission data 2
Transmission data 1
Transmission data 0
SFDB register
SFDB
2, 1, 0
SIRB
SIO
SIRBE
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SFA register
SI3n pin
3, 2, 1, 0
SIO Load/Store
FIFO pointer
SFP
Write FIFO
pointer
Read FIFO
pointer
INC
INC
INC
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