upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 644

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(3)
Caution:
Remark:
16.11.2 CAN stop mode
The CAN stop mode can be used to set the CAN controller to standby mode to reduce power consump-
tion. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the
CAN stop mode puts the CAN module in the CAN sleep mode.
The CAN stop mode can only be released by writing 01B to the PSMODE[1:0] bits of the CnCTRL reg-
ister and not by a change in the CAN bus state. No message is transmitted even when transmission
requests are issued or pending.
(1)
Caution:
644
Releasing CAN sleep mode
The CAN sleep mode is released by the following events.
• When the CPU writes 00B to the PSMODE[1:0] bits of the CnCTRL register
• A falling edge at the CAN reception pin (CRXDn) (i.e. the CAN bus level shifts from recessive to
After releasing the sleep mode, the CAN module returns to the operation mode from which the
CAN sleep mode was requested and the PSMODE[1:0] bits of the CnCTRL register are reset to
00B. If the CAN sleep mode is released by a change in the CAN bus state, the CINTS5 bit of the
CnINTS register is set to 1, regardless of the CIE bit of the CnIE register. After the CAN module is
released from the CAN sleep mode, it participates in the CAN bus again by automatically detect-
ing 11 consecutive recessive-level bits on the CAN bus.
When a request for transition to the initialization mode is made while the CAN module is in the
CAN sleep mode, that request is ignored; the CPU has to be released from sleep mode by soft-
ware first before entering the initialization mode.
Entering CAN stop mode
A CAN stop mode transition request is issued by writing 11B to the PSMODE[1:0] bits of the
CnCTRL register.
A CAN stop mode request is only acknowledged when the CAN module is in the CAN sleep mode.
In all other modes, the request is ignored.
dominant)
Even if the falling edge belongs to the SOF of a receive message, this message will
not be received and stored. If the CPU has turned off the clock to the CAN while the
CAN was in sleep mode, later on the CAN sleep mode will not be released and
PSMODE[1:0] bits will continue to be 01B unless the clock for the CAN is provided
again. In addition to this, the receive message will not be received afterwards.
n = 0, 1
m = 0 to 31
To set the CAN module to the CAN stop mode, the module must be in the CAN sleep
mode. To confirm that the module is in the sleep mode, check that PSMODE[1:0] =
01B, and then request the CAN stop mode. If a bus change occurs at the CAN recep-
tion pin (CRXD) while this process is being performed, the CAN sleep mode is auto-
matically released. In this case, the CAN stop mode transition request cannot be
acknowledged.
Chapter 16 FCAN Controller
User’s Manual U16702EE3V2UD00