upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 496

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(6)
1.
2.
3.
4.
5.
6.
7.
496
CSIBUF-empty
CTXE, CRXE
SCK3 (input)
SFDB write
Single Buffer Transfer Mode (Slave Mode, Transmit/Receive Mode)
MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS
inactive disabled (CSMD = 0), CKP = 0, DAP = 1, transmission data length of 8 bits
(CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”:
CSIBUF_1
CSIBUF_2
Set the CSIM register's POWER bit to 1 to enable the supply of the Queued CSI operation clock.
Set the CSIC and CSIL registers to specify the transfer mode.
Write “1” in the SFA register's FPCLR bit to clear all FIFO pointers.
Specify the transmit mode using the CSIM register's TRMD, DIR, and CSIT bits; at the same time,
set the CTXE and CRXE bits to 1 to enable the transmit/receive operation.
Make sure that the SFA register's SFFUL bit is set to 0, then write transmission data in the SFDB
register. (In the slave mode, there is no need to set data in the SFCS register, as the chip select
pins CS3n[3:0] are not used.)
Check for a reception to be completed (e.g. by monitoring the INTC3nI interrupt). If so, read the
SIRB register.
Repeat steps (5) and (6) until the last element is send/received and read from the SIRB register.
Set the CSIM register's CTXE and CRXE bits to 0 to disable the transmit/receive operation (end of
transmit/receive operation).
CSIBUF_0
SIRB read
CS3n[3:0]
INTC3nI
SFP3-0
CSOT
SIRB
SO3
Figure 14-30: Single Buffer Transfer Mode (Slave, Transmit/Receive) Timing
(1)
SI3
(2)(3)
"inactive level"
0
(4)
(5)
0
1
1
55H
1
1
0
0
(5)
Chapter 14 Queued CSI (CSI30, CSI31)
1
0
2
0
1 1
AAH
1
User’s Manual U16702EE3V2UD00
Wait insertion by SIRB-full before
INTC3nI/SIRB store/CSOT clear
0
0 0
1
1
1
1
CCH
0
0 0
1
0
1
1
0
0
1 1
1
0
0
(6)
Wait insertion
by CSIBUF-empty
0
96H
(5)
0
1
1
33H
0
0 0
1
(6)
1
1 1
Wait insertion
by CSIBUF-empty
0 0
0 0
1 1
1
0
(6)
(7)
99H