upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 265

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upd70f3402

Manufacturer Part Number
upd70f3402
Description
32-/16-bit Single-chip Microcontroller With Can Interface
Manufacturer
Renesas Electronics Corporation.
Datasheet
(4)
Cautions: 1. Rewrite bits TPnIS3 to TPnIS0 when TPnCE = 0 (the same value can be written
Remark:
TPnIOC1
Symbol
TMPn dedicated I/O control register 1 (TPnIOC1)
The TPnIOC1 register is an 8-bit register that controls the valid edge for the external input signals
(TIPn0 and TIPn1).
This register can be read and written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
TPnIS3
TPnIS1
0
0
1
1
0
0
1
1
Address: TP0IOC1: FFFFF593H, TP1IOC1: FFFFF5A3H
2. Bits TPnIS3 to TPnIS0 are valid only in the free-running mode and pulse width
3. If used as the capture input, be sure to set the corresponding alternate-function
n = 0 to 3
7
Figure 7-8: TMPn Dedicated I/O Control Register 1 (TPnIOC1) Format
0
when TPnCE = 1.). If rewriting was mistakenly performed, clear TPnCE to 0 and
then set the bits again.
measurement mode. In all the other modes, capture operation is not performed.
pins TPnOE1 and TPnOE0 of the TPnIOC0 register to “Timer output is disabled”
and set the capture input valid edge. Then set the corresponding alternate-func-
tion port to input mode.
TPnIS2
TPnIS0
TP2IOC1: FFFFF5B3H, TP3IOC1: FFFFF5C3H
0
1
0
1
0
1
0
1
6
0
Chapter 7 16-Bit Timer/Event Counter P
No edge detection (capture operation is invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation is invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
5
0
User’s Manual U16702EE3V2UD00
4
0
TPnIS3 TPnIS2 TPnIS1 TPnIS0
Capture input (TIPn0) valid edge detection
Capture input (TIPn1) valid edge setting
3
2
1
0
FFFFF5C3H
FFFFF593H
Address
to
R/W
R/W 00H
After
reset
265

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