upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 838

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

A.2 Instruction Set (In Alphabetical Order)
ADD
ADDI
AND
ANDI
Bcond
BSH
BSW
CALLT
CLR1
CMOV
CMP
CTRET
DI
DISPOSE
DIV
DIVH
DIVHU
DIVU
EI
HALT
HSW
JARL
JMP
838
Mnemonic
(1/4)
reg1,reg2
imm5,reg2
imm16,reg1,reg2
reg1,reg2
imm16,reg1,reg2
disp9
reg2,reg3
reg2,reg3
imm6
bit#3, disp16[reg1]
reg2,[reg1]
cccc,imm5,reg2,
reg3
cccc,reg1,reg2,
reg3
reg1,reg2
imm5,reg2
imm5,list12
imm5,list12,[reg1]
reg1,reg2,reg3
reg1,reg2
reg1,reg2,reg3
reg1,reg2,reg3
reg1,reg2,reg3
reg2,reg3
disp22,reg2
[reg1]
Operand
Note 1
Note 5
Note 7
rrrrr001110RRRRR GR[reg2]←GR[reg2] + GR[reg1]
rrrrr010010iiiii GR[reg2]←GR[reg2] + sign-extend(imm5)
rrrrr110000RRRRR
iiiiiiiiiiiiiiii
rrrrr001010RRRRR GR[reg2]←GR[reg2] AND GR[reg1]
rrrrr110110RRRRR
iiiiiiiiiiiiiiii
ddddd1011dddcccc
rrrrr11111100000
wwwww01101000010
rrrrr11111100000
wwwww01101000000
0000001000iiiiii
10bbb111110RRRRR
dddddddddddddddd
rrrrr111111RRRRR
0000000011100100
rrrrr111111iiiii
wwwww011000cccc0
rrrrr111111RRRRR
wwwww011001cccc0
rrrrr001111RRRRR result←GR[reg2] – GR[reg1]
rrrrr010011iiiii result←GR[reg2] – sign-extend(imm5)
0000011111100000
0000000101000100
0000011111100000
0000000101100000
0000011001iiiiiL
LLLLLLLLLLL00000
0000011001iiiiiL
LLLLLLLLLLLRRRRR
rrrrr111111RRRRR
wwwww01011000000
rrrrr000010RRRRR GR[reg2]←GR[reg2] ÷ GR[reg1]
rrrrr111111RRRRR
wwwww01010000000
rrrrr111111RRRRR
wwwww01010000010
rrrrr111111RRRRR
wwwww01011000010
1000011111100000
0000000101100000
0000011111100000
0000000100100000
rrrrr11111100000
wwwww01101000100
rrrrr11110dddddd
ddddddddddddddd0
00000000011RRRRR PC←GR[reg1]
Opcode
Appendix A
User’s Manual U16702EE3V2UD00
GR[reg2]←GR[reg1] + sign-extend(imm16)
GR[reg2]←GR[reg1] AND zero-extend(imm16)
if conditions are satisfied
then PC←PC+sign-extend(disp9)
GR[reg3]←GR[reg2] (23: 16) ll GR[reg2] (31: 24) ll
GR[reg3]←GR[reg2] (7: 0) ll GR[reg2] (15: 8) ll
CTPC←PC + 2(return PC)
CTPSW←PSW
adr←CTBP+zero-extend(imm6 logically shift left by 1)
PC←CTBP+zero-extend(Load-memory(adr,Half-word))
adr←GR[reg1] + sign-extend(disp16)
Z flag
Store-memory-bit(adr,bit#3,0)
adr←GR[reg1]
Z flag
Store-memory-bit(adr,reg2,0)
if conditions are satisfied
if conditions are satisfied
PC←CTPC
PSW←CTPSW
PSW.ID←1
sp←sp + zero-extend(imm5 logically shift left by 2)
GR[reg in list12]←Load-memory(sp,Word)
sp←sp + 4
repeat 2 steps above until all regs in list12 are loaded
sp←sp + zero-extend(imm5 logically shift left by 2)
R[reg in list12]←Load-memory(sp,Word)
sp←sp + 4
repeat 2 steps above until all regs in list12 are loaded
PC←GR[reg1]
GR[reg2]←GR[reg2] ÷ GR[reg1]
GR[reg3]←GR[reg2] % GR[reg1]
GR[reg2]←GR[reg2] ÷ GR[reg1]
GR[reg3]←GR[reg2] % GR[reg1]
GR[reg2]←GR[reg2] ÷ GR[reg1]
GR[reg3]←GR[reg2] % GR[reg1]
GR[reg2]←GR[reg2] ÷ GR[reg1]
GR[reg3]←GR[reg2] % GR[reg1]
PSW.ID←0
Stop
GR[reg3]←GR[reg2](15: 0) ll GR[reg2] (31: 16)
GR[reg2]←PC + 4
PC←PC + sign-extend(disp22)
then GR[reg3]←sign-extended(imm5)
else GR[reg3]←GR[reg2]
then GR[reg3]←GR[reg1]
else GR[reg3]←GR[reg2]
←Not(Load-memory-bit(adr,bit#3))
←Not(Load-memory-bit(adr,reg2))
GR[reg2] (7: 0) ll GR[reg2] (15: 8)
GR[reg2] (23: 16) ll GR[reg2] (31: 24)
Instruction Set List
Operation
Note 6
Note 6
Note 6
When conditions
are satisfied
When conditions
are not satisfied
Note
Note
Note
N+1
Note
N+3
Note
35 35 35
35 35 35
35 35 35
34 34 34
34 34 34
1
1
1
1
1
2
1
1
1
4
3
3
1
1
1
1
3
1
1
1
1
2
3
2
3
3
4
4
Execution
i
Clock
N+1
N+3
Note
Note
Note
Note
Note
1
1
1
1
1
2
1
1
1
4
3
3
1
1
1
1
3
1
1
1
1
2
3
2
3
3
4
4
r
N+1
N+3
Note
Note
Note
Note
Note
1
1
1
1
1
2
2
1
1
1
4
3
3
3
3
1
1
1
1
3
1
4
4
1
1
1
2
3
l
CY OV S
R
×
×
×
×
×
×
×
×
R
×
×
×
0
0
0
0
×
×
×
×
×
×
0
Flags
R
×
×
×
×
0
×
×
×
×
×
×
×
×
×
R
Z SAT
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
R
×