upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 699

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Notes: 1. Lower default priority
Caution:
Interrupt request o
Interrupt request s
Interrupt request i
Interrupt request l
Figure 17-8: Example of Processing in Which Another Interrupt Request Is Issued
2. Higher default priority
To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers
must be saved before executing the EI instruction. When returning from multiple
interrupt servicing, restore the values of EIPC and EIPSW after executing the DI
instruction.
(level 2)
(level 2)
(level 3)
(level 1)
Main routine
Chapter 17 Interrupt/Exception Processing Function
EI
Interrupt request n
request p
Interrupt request u
Interrupt
(level 2)
Interrupt request k
While an Interrupt Is Being Serviced (2/2)
Interrupt
request j
(level 3)
(level 1)
(level 3)
(level 1)
request m
(level 2)
(level 2)
User’s Manual U16702EE3V2UD00
request t
Interrupt
Interrupt
EI
Servicing of o
EI
request q
Interrupt
(level 1)
Servicing of i
Servicing of j
Servicing of s
Note 1
Servicing of l
Servicing of n
Servicing of u
Note 2
Servicing of t
Servicing of m
EI
Servicing of p
request r
Interrupt
(level 0)
Servicing of k
EI
Servicing of q
Pending interrupt requests t and u are
acknowledged after servicing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.
If levels 3 to 0 are acknowledged
Interrupt request j is held pending because its
priority is lower than that of i.
k that occurs after j is acknowledged because it
has the higher priority.
Interrupt requests m and n are held pending
because servicing of l is performed in the interrupt
disabled status.
Pending interrupt requests are acknowledged after
servicing of interrupt request l.
At this time, interrupt request n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Servicing of r
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