upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 252

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

6.6 Usage
6.6.1 To use PLL1
After RESET has been released, the default mode is PLL0 mode (F
operating mode change to PLL1 mode, register access must keep below mentioned order.
Caution:
The follow table shows the divide and PLL0 time value.
The follow table shows the divide and PLL1 time value.
252
12h
11h (Default)
18h
10h (Default)
18h
OCKS0 register (h)
OCKS1 register (h)
• (When use PLL1 function as master clock and PLL0 for peripheral clock)
1) Setting OCKS1 register
2) Setting CKC register
3) PLLCTL1 register =
4) MPCCTL register =
4) MPCCTL register =
5) MPCCTL register <= 88H write (MPCCTL: SELPLL bit = MCKSEL bit =1)
• (When use PLL1 function as master clock and peripheral clock)
1) Setting OCKS1 register
2) Setting CKC register
3) PLLCTL1 register =
4) MPCCTL register =
4) MPCCTL register =
5) MPCCTL register <= 8DH write (MPCCTL: SELPLL bit = MCKSEL bit = PCKSEL bit =
STPPLL0 bit = 1)
Before using the STOP/IDLE mode for power saving operation, the user must first
reduce CPU operating frequency to 20 MHz using PCC register.
03h
03h (Default)
02h
03h
03h
03h
CKC register (h)
CKC register (h)
Table 6-1: Divide and PLL0 Time Value
Table 6-2: Divide and PLL1 Time Value
00H write
08H write (MPCCTL: MCKSEL bit = 1)
00H write
08H write (MPCCTL: MCKSEL bit = 1)
00H write
00H write
User’s Manual U16702EE3V2UD00
Chapter 6 Clock Generator
PLL time value
PLL time value
(MPCCTL: SELPLL bit = 0)
(MPCCTL: SELPLL bit = 0)
10
3
4
6
2
5
Xtal = 4 MHz
Xtal = 4 MHz
12
16
24
20
40
8
PLL_MCKSEL
Xtal = 6 MHz
Xtal = 6 MHz
prohibited
f
f
Setting
X
X
(MHz)
(MHz)
18
24
36
12
30
= 4 × f
X
). When
Xtal = 8 MHz
Xtal = 8 MHz
prohibited
prohibited
Setting
Setting
24
32
16
40