upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 598

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Remarks: 1. Detection of a valid receive message frame is not dependent upon storage in the
Caution:
Remark:
(b) Write
598
Other than above
PSMODE1 PSMODE0
OPMODE2 OPMODE1 OPMODE0
VALID
Set CCERC
0
0
1
1
0
0
0
0
1
1
0
1
2. Clear the VALID bit (0) before changing the initialization mode to an operation mode.
3. If only two CAN nodes are connected to the CAN bus with one transmitting a message
4. The VALID bit is read-only in the CAN sleep mode or CAN stop mode.
5. To clear the VALID bit, set the Clear VALID bit to 1 first and confirm that the VALID bit is
Transition to and from the CAN stop mode must be made via CAN sleep mode. A
request for direct transition to and from the CAN stop mode is ignored.
The OPMODE[2:0] bits are read-only in the CAN sleep mode or CAN stop mode.
1
Other than above
Figure 16-28: CAN Module Control Register (CnCTRL) Format (3/4)
receive message buffer (data frame) or transmit message buffer (remote frame).
frame in the normal mode and the other in the reception mode, the VALID bit is not set
to 1 before the transmitting node enters the error passive state.
cleared. If it is not cleared, perform clearing processing again.
A valid message frame has not been received since the VALID bit was last cleared to 0.
A valid message frame has been received since the VALID bit was last cleared to 0.
0
1
0
1
0
0
1
1
0
0
CCERC bit is set to 1.
CCERC bit is not changed.
No power save mode is selected.
CAN sleep mode
Setting prohibited
CAN stop mode
0
1
0
1
0
1
Chapter 16 FCAN Controller
User’s Manual U16702EE3V2UD00
Valid receive message frame detection bit
No operation mode is selected (CAN module is in the initialization
mode).
Normal operation mode
Normal operation mode with automatic block transmission func-
tion (normal operation mode with ABT)
Receive-only mode
Single-shot mode
Self-test mode
Setting prohibited
Setting of CCERC bit
Power save mode
Operation mode