upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 522

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

15.5 Transfer Modes
In the following examples it is assumed that TCS is set as “1” for all DMA channels.
15.5.1 Single transfer mode
In Single transfer mode, the DMA releases the bus after each transfer. If there is a subsequent DMA
transfer request, the transfer is performed again when the bus becomes available again. This operation
continues until the transfer counter is cleared to 0 and the internal TC signal is generated.
When the DMA has released the bus, if another higher priority DMA transfer request is issued, the
higher priority DMA request always takes precedence.
A Single transfer mode example is shown in Figures 15-13 and 15-14.
Figure 15-13 shows the transfers of DMA0 with DMBC0 set to 3 at the beginning of the transfers:
Figure 15-14 shows the Single Transfer mode with DMA requests on multiple DMA channels. The
number of transfers is set to 2 for all channels (DMBCn=1) at the beginning.
After each bus release, the DMA controller checks which pending DMA request has the highest priority,
delaying the execution of the lower-prioritized DMA transfer accordingly.
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Note: The bus is always released.
DMMRQ0
DMMRQ2
DMMRQ4
INTDMA2
INTDMA4
INTDMA0
Note: The bus is always released.
DMMRQ0
INTDMA0
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Figure 15-14: Single Transfer Mode Example (3 Channels)
Figure 15-13: Single Transfer Mode Example (1 Channel)
CPU DMA4
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Chapter 15 DMA Functions (DMA Controller)
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User’s Manual U16702EE3V2UD00
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