upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 498

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upd70f3402

Manufacturer Part Number
upd70f3402
Description
32-/16-bit Single-chip Microcontroller With Can Interface
Manufacturer
Renesas Electronics Corporation.
Datasheet
(8)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Set the CSIM register's CRXE bit to 0 to disable the receive operation (end of receive operation).
Remark:
498
CSIB
SFDB write
FIFO Buffer Transfer Mode (Master Mode, Receive Only Mode)
MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS
inactive disabled (CSMD = 0), CKP = 0, DAP = 1, transmission data length of 8 bits
(CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”:
Set the CSIM register's POWER bit to 1 to enable the supply of the Queued CSI operation clock.
Set the CSIC and CSIL registers to specify the transfer mode.
Write “1” in the SFA register's FPCLR bit to clear all FIFO pointers.
Specify the transfer mode using the CSIM register's TRMD, DIR, and CSIT bits; at the same time,
set the CRXE bit to 1 to enable the receive operation.
Set the number of receive-data items in the SFN register's SFN[3:0] bits.
Make sure that the SFA register's SFFUL bit is set to 0, then write chip-select data and dummy
transmission data in the SFCS and SFDB registers in this order (start-of-receive trigger).
Wait for the receptions to be completed (e.g. by monitoring the INT3C3nI interrupt).
Read the received data by multiple read of the SIRB register (= sequential read from the FIFO).
Write “1” in the SFA register's FPCLR bit and clear all FIFO pointers for the next transmission.
To continue reception, repeat steps (5) - (9).
CSIBUF_1
CSIBUF_2
CSIBUF_0
SIRB read
UF-empty
CS3n[3:0]
INTC3nI
SFN3-0
SFP3-0
CRXE
CSO T
SCK3
(1)
SI3
The SO3n pin is invalid and maintains its signal level, as the output latch is disabled.
Figure 14-32: FIFO Buffer Transfer Mode (Master, Receive Only) Timing
(2)(3)
"active-L"
(4)
(5)
(6)
3H
0H
0
dummy
1
0
(6)
Chapter 14 Queued CSI (CSI30, CSI31)
CS 0
1
dumm y
0
1
User’s Manual U16702EE3V2UD00
0
1
1H
1
55H
0
Wait insertion
by CSIBUF-empty
1
CS 1
0
1
0
1
0
2H
AAH
(6)
1 1
dummy
0 0
CS 2
1 1
0 0
(7)
CCH
(8)
3H
(8)
(8)
(9)
(10)
0H

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