upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 521

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

15.4.4 DMA transfer end
At the end of a DMA transfer, the EN bit is cleared to 0 by the hardware and a DMA interrupt
(INTDMAn) is generated when TCS is set as 1.
The interrupt generation for TCS=0 and TCS=1 is as follows:
(1)
(2)
TCS = 0:
When TCS is set as 0, the DMA interrupt is a direct mirror the DMA trigger signal (e.g. the on-chip
peripheral I/O interrupt).
TCS = 1:
When TCS bit is set as 1, the DMA interrupt is generated when the last DMA transfer request is
executed.
Figure 15-12 illustrates the timing of INTDMAn for the two TCS settings. As mentioned before, the
mirror function is not required for V850E/RS1, therefore it is highly recommended NOT to use a
setting of TCS=0.
DMMRQ0
INTDMA0
Last DMA
Last DMA
DMMRQ0
INTDMA0
TCS=0:
TCS=1:
transfer
transfer
CPU
CPU
CPU
CPU
Figure 15-12: TCS Bit and INTDMAn Generation
Chapter 15 DMA Functions (DMA Controller)
CPU
CPU
User’s Manual U16702EE3V2UD00
CPU DMA0 CPU DMA0
CPU DMA0 CPU DMA0
CPU
CPU
CPU DMA0 CPU DMA0
CPU DMA0 CPU DMA0
CPU
CPU
CPU
CPU
CPU
CPU
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