upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 28

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

28
Table 15-2:
Table 15-3:
Table 16-1:
Table 16-2:
Table 16-3:
Table 16-4:
Table 16-5:
Table 16-6:
Table 16-7:
Table 16-8:
Table 16-9:
Table 16-10: Bit Stuffing .................................................................................................................... 539
Table 16-11: Error Types................................................................................................................... 540
Table 16-12: Output Timing of Error Frame....................................................................................... 541
Table 16-13: Types of Error States.................................................................................................... 542
Table 16-14: Error Counter................................................................................................................ 543
Table 16-15: List of CAN Controller Registers................................................................................... 552
Table 16-16: Register Access Type................................................................................................... 553
Table 16-17: CAN Module Register Bit Configuration ....................................................................... 584
Table 16-18: CAN Global Register Bit Configuration......................................................................... 586
Table 16-19: Message Buffer Register Bit Configuration .................................................................. 587
Table 16-20: List of CAN Module Interrupt Sources .......................................................................... 647
Table 16-21: Settable Bit Rate Combinations.................................................................................... 653
Table 16-22: Representative Examples of Baud Rate Settings (f
Table 16-23: Representative Examples of Baud Rate Settings (f
Table 17-1:
Table 17-2:
Table 17-3:
Table 17-4:
Table 17-5:
Table 17-6:
Table 17-7:
Table 18-1:
Table 18-2:
Table 18-3:
Table 18-4:
Table 18-5:
Table 18-6:
Table 18-7:
Table 18-8:
Table 18-9:
Table 19-1:
Table 19-2:
Table 19-3:
Table 21-1:
Table 21-2:
Table 21-3:
Table 21-4:
Table 21-5:
Table 21-6:
Table 22-1:
Table 22-2:
Table 25-1:
Table 25-2:
Table 26-1:
Table 29-1:
Operation Status of Clock Monitor (When CLM.CLME Bit = 1,
During Ring-OSC Operation) (CKSEL Connected to Ring-OSC)................................. 791
Transfer Targets ........................................................................................................... 520
Comparison of DMA Transfer Modes ........................................................................... 524
Overview of Functions .................................................................................................. 526
Frame Types ................................................................................................................ 529
RTR Frame Settings..................................................................................................... 531
Frame Format Setting (IDE Bit) and Number of Identifier (ID) Bits .............................. 532
Data Length Setting...................................................................................................... 532
Operation in Error Status.............................................................................................. 536
Definition of Error Frame Fields.................................................................................... 537
Definition of Overload Frame Fields ............................................................................. 538
Determining Bus Priority............................................................................................... 539
Interrupt/Exception Source List .................................................................................... 685
Interrupt Control Register (xxICn)................................................................................. 702
Watchdog Timer 2 Clock Selection .............................................................................. 708
Valid Edge Specification............................................................................................... 709
Valid Edge Specification............................................................................................... 710
Valid Edge Specification............................................................................................... 711
Valid Edge Specification............................................................................................... 712
Standby Modes............................................................................................................. 723
Operation After Releasing HALT Mode by Interrupt Request ...................................... 727
Operation Status in HALT Mode................................................................................... 728
Operation After Releasing IDLE1 Mode by Interrupt Request...................................... 730
Operation Status in IDLE1 Mode.................................................................................. 730
Operation After Releasing IDLE2 Mode by Interrupt Request...................................... 732
Operation Status in IDLE2 Mode.................................................................................. 732
Operation After Releasing STOP Mode by Interrupt Request...................................... 735
Operation Status in STOP Mode .................................................................................. 735
Hardware Status on RESET Pin Input.......................................................................... 741
Hardware Status During WDT2RES Signal Generation............................................... 743
Hardware Status During Reset Operation by Low-Voltage Detector............................ 745
Signal Generation of Dedicated Flash Programmer (PG-FP4) .................................... 755
Relationship Between FLMD0 and FLMD1 Pins and Operation Mode ........................ 757
Pins Used by each Serial Interface .............................................................................. 758
List of Communication Modes ...................................................................................... 764
Flash Memory Control Command................................................................................. 765
Response Commands .................................................................................................. 765
ID Code ........................................................................................................................ 770
Pin Functions of Connector for Emulator Connection (Target System Side) ............... 776
Configuration of Clock Monitor ..................................................................................... 789
CRC Configuration ....................................................................................................... 793
Soldering Conditions .................................................................................................... 833
User’s Manual U16702EE3V2UD00
CANMOD
CANMOD
= 8 MHz) ......................... 656
= 16 MHz) ....................... 658