upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 701

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

17.3.4 Interrupt control register (xxICn)
An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the
control conditions for each maskable interrupt request.
This register can be read or written in 8-bit or 1-bit units.
Note: The flag xxlFn is reset automatically by the hardware if an interrupt request is acknowledged.
Remark:
Caution:
The addresses and bits of the interrupt control registers are as follows.
xxICn
After reset: 47H
xx: Identification name of each peripheral unit (Refer to Table 17-2, “Interrupt Control
Register (xxICn),” on page 702)
n: Peripheral unit number (Refer to Table 17-2, “Interrupt Control Register (xxICn),” on
page 700)
Disable interrupts (DI) or mask the interrupt to read the xxICn bit.
If the xxIFn bit is read while interrupts are enable (EI) or while the interrupt is
unmasked, the correct value may not be read when acknowledging an interrupt are
reading the bit conflict.
xxPRn2
xxMKn
xxIFn
xxIFn
<7>
Figure 17-10: Interrupt Control Register (xxICn) Format
0
1
0
1
0
0
0
0
1
1
1
1
Chapter 17 Interrupt/Exception Processing Function
Interrupt request not issued
Interrupt request issued
Interrupt servicing enabled
Interrupt servicing disabled (pending)
xxPRn1
xxMKn
<6>
User’s Manual U16702EE3V2UD00
0
0
1
1
0
0
1
1
xxPRn0
R/W
5
0
0
1
0
1
0
1
0
1
Interrupt request flag
4
0
Interrupt mask flag
Address: FFFFF110H to FFFFF18EH
Interrupt priority specification bit
Specifies level 0 (highest).
Specifies level 7 (lowest).
3
0
Specifies level 1.
Specifies level 2.
Specifies level 3.
Specifies level 4.
Specifies level 5.
Specifies level 6.
xxPRn2
Note
2
xxPRn1
1
xxPRn0
0
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