upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 479

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Chapter 14 Queued CSI (CSI30, CSI31)
14.3.4 Slave Mode
When the CKS[2:0] bits in CSIC are set to [1,1,1], the Queued CSI operates in slave mode. In slave
mode, the SCK3 serial clock pin becomes input and another device is the CSI communication master.
The baud rate generator “BRG” is recommended to be disabled by setting bits MDL[2:0] to [0,0,0] when
using slave mode. Also, the chip select pin CS3n[3:0] outputs are not available in slave mode, as they
are only available in master mode.
The example below shows the communication in slave mode for 8 data bits, CKP=0, DAP=0 and MSB
first:
Figure 14-14: Slave Mode
SCK3
(input)
SI3
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO3
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
14.3.5 Master Mode
When the CKS[2:0] bits in CSIC are not set to [1,1,1], the Queued CSI operates in master mode. In
master mode, the SCK3 pin is configured as output and the serial communication clock is generated by
the Queued CSI module. The SCK3 pin’s default value is “1” when CKP = 1, and is default “0” when
CKP = 0. The CS3n[3:0] pin outputs are available in master mode.
The example below shows the communication in master mode for 8 data bits, CKP=0, DAP=0 and MSB
first:
Figure 14-15: Master Mode
SCK3
(output)
SI3
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO3
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
User’s Manual U16702EE3V2UD00
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