upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 640

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

During ABT, the priority of the transmission ID is not searched. The data of message buffers 0 to 7 is
sequentially transmitted. When transmission of the data frame from message buffer 7 has been com-
pleted, the ABTTRG bit is automatically cleared to 0 and the ABT operation is finished.
If the RDY bit of an ABT message buffer is cleared during ABT, no data frame is transmitted from that
buffer, ABT is stopped, and the ABTTRG bit is cleared. After that, transmission can be resumed from
the message buffer where ABT stopped, by setting the RDY and ABTTRG bits to 1 by software. To not
resume transmission from the message buffer where ABT stopped, the internal ABT engine can be
reset by setting the ABTCLR bit to 1 while ABT mode is stopped and ABTTRG is cleared to 0. In this
case, transmission is started from message buffer 0 if the ABTCLR bit is cleared to 0 and then the ABT-
TRG bit is set to 1.
An interrupt can be used to check if data frames have been transmitted from all the message buffers for
ABT. To do so, the IE bit of the CnMCTRLm register of each message buffer except the last message
buffer needs to be cleared (0).
If a transmit message buffer other than those used by the ABT function (message buffer 8 to 31) is
assigned to a transmit message buffer, the priority of the message to be transmitted is determined by
the priority of the transmission ID of the ABT message buffer whose transmission is currently held
pending and the transmission ID of the message buffers other than those used by the ABT function.
Transmission of a data frame from an ABT message buffer is not recorded in the transmit history list
(THL).
Cautions: 1. To resume the normal operation mode with ABT from the message buffer 0, set
640
2. If the automatic block transmission engine is cleared by setting the ABTCLR bit
3. Do not set the ABTTRG bit in the initialization mode. If the ABTTRG bit is set in
4. Do not set TRQ of the ABT message buffers to 1 by software in the normal opera-
5. The CnGMABTD register is used to set the delay time that is inserted in the
6. If a transmission request is made for a message other than an ABT message and
7. Do not clear the RDY bit to 0 when ABTTRG = 1.
8. If a message is received from another node in the normal operation mode with
the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0. If the ABTCLR bit is set
to 1 while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed.
to 1, the ABTCLR bit is automatically cleared immediately after the processing of
the clearing request is completed.
the initialization mode, the proper operation is not guaranteed after the mode is
changed from the initialization mode to the ABT mode.
tion mode with ABT. Otherwise, the operation is not guaranteed.
period from completion of the preceding ABT message to setting of the TRQ bit
for the next ABT message when the transmission requests are set in the order of
message numbers for each message for ABT that is successively transmitted in
the ABT mode. The timing at which the messages are actually transmitted onto
the CAN bus varies depending on the status of transmission from other stations
and the status of the setting of the transmission request for messages other than
the ABT messages (message buffer 8 to 31).
if no delay time is inserted in the interval in which transmission requests for ABT
are automatically set (CnGMABTD = 00H), messages other than ABT messages
are transmitted. At this time, transmission does not depend on the priority of the
ABT message.
ABT, the message may be transmitted after the time of one frame has elapsed
(when CnGMABTD register = 00H).
Chapter 16 FCAN Controller
User’s Manual U16702EE3V2UD00