upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 491

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

14.4 Operating Procedure
(1)
1.
2.
3.
4.
5.
6.
CSIB
SFDB write
Single Buffer Transfer Mode (Master Mode, Transmit Only Mode)
MSB first (DIR = 0), no INTC3nI delay (CSIT=0), transmission wait disabled (CSWE = 0),
CS inactive disabled (CSMD = 0), CKP = 0, DAP = 0, transmission data length of 8 bits
(CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”:
Set the CSIM register's POWER bit to 1 to enable the supply of the Queued CSI operation clock.
Set the CSIC and CSIL registers to specify the transfer mode.
Write “1” in the SFA register's FPCLR bit to clear all FIFO pointers.
Specify the transfer mode using the CSIM register's TRMD, DIR, and CSIT bits; at the same time,
set the CTXE bit to 1 to enable transmission.
Make sure that the SFA register's SFFUL bit is set to 0, then write chip-select data and
transmission data in the SFCS and SFDB registers in this order.
Repeat step (5) until the last element to be transmitted is written in the SFCS/SFDB registers.
Set the CSIM register's CTXE bit to 0 to disable transmission (end of transmission).
CSIBUF_0
CSIBUF_1
CSIBUF_2
UF-empty
CS3n[3:0]
INTC3nI
SFP3-0
CSOT
CTXE
SCK3
SO3
(1)
Figure 14-25: Single Buffer Transfer Mode (Master, Transmit Only) Timing
(2)(3)
"active-L"
0
(4)
(5)
1
55H
0
1
0
(5)
Chapter 14 Queued CSI (CSI30, CSI31)
CS 0
User’s Manual U16702EE3V2UD00
1
2
0
1
AAH
0
1 1
1
0
1
CS 1
0
1
0
Wait insertion
by CSIBUF empty
1
0
0
(5)
1
CCH
1 1
0 0
CS 2
1 1
0
0
0
(6)
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