upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 234

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

6.2 Configuration
(1)
(2)
(3)
(4)
(5)
234
PSMR (STOP)
X1
X2
PCC.MFR
Main clock oscillator (Main OSC)
The main resonator oscillates the following frequencies (f
• In clock-through mode
• In PLL mode
PLL
This circuit multiplies the clock generated by the main clock oscillator (f
It operates in two modes: clock-through mode in which f
multiplied clock is output. These modes can be selected by using the SELPLL bit of the Main
peripheral clock control register (MPCCTL). Operation of the PLL can be started or stopped by the
STPPLL bit of MPCCTL register.
Ring-OSC
Outputs a frequency (f
Prescaler 1 (PRS1)
This prescaler divides the clock to be supplied to the WDT2 and the on-chip peripheral functions.
Prescaler 2 (PRS2)
This circuit divides main clock f
clock and system clock (f
f
output from the CLKOUT pin.
f
CLK
CPU
MPCCTL.STPPLL0
MPCCTL.STPPLL1
MPCCTL.MCKSEL
MPCCTL.PCKSEL
Main OSC
f
f
X
X
PSMR (IDLE2)
CKC.CKDIV0
CKC.CKDIV1
is supplied to the interrupt controller INTC, ROM controller, ROM and RAM blocks. It can be
= 4 to 8 MHz (internal f
= 4 to 8 MHz (internal f
is the clock supplied to CPU.
OCSK0
OCSK1
f
X
PLL0 (×12)
PLL1 (×10)
PLL
t
PLL
MPCCTL.SELPLL
BRGC
_MCKSEL_CKDIV
R
) of 100 to 400 kHz.
CLK
t
PLL
XX
XX
).
_MCKSEL
Figure 6-1: Clock Generator
OCKS2
XX
User’s Manual U16702EE3V2UD00
Chapter 6 Clock Generator
= 4 to 8 MHz)
t
PLL
= 4 to 40 MHz (µPD70F3403 and µPD70F3403A)
= 4 to 32 MHz (µPD70F3402))
_PCKSEL
(f
XX
Output
control
f
XX
Output
control
PSMR (IDLE1)
, f
Standby
XX
control
/2, f
PCLM.PCKm
PCLM.PCLE
OCKS3
PLL
aFCAN, CSI3n
Extended clock for CSIBm
XX
/4, f
XX
/8, f
PRS1
PRS2
X
X
is output as is, and PLL mode in which a
XX
PCC.CKm
).
Ring-OSC
/16, f
f
f
XX
XX
f
f
f
XX
XX
XX
/32
/16
f
/8
/4
/2
XX
XX
f
R
Peripherals
WDT2
/32) to provide the CPU (f
X
).
PSMR (HALT)
1/8
CCLS.CCLSF
Standby
control
f
f
CPU
CLK
CPUCLK
SystemCLK
WDT2
CPU)