upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 791

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

25.4 Operation of Clock Monitor
This section explains the functions of the clock monitor. The start and stop conditions are as follows.
Notes: 1. Ring-OSC can be stopped by setting the RSTOP bit of the RCM register to 1
(1)
Main clock
Ring-OSC clock
Reset
CPU operation
reset signal
Main clock
<Start condition>
Enabling operation by setting bit 0 (CLME) of the clock monitor mode register to 1
<Stop condition>
• While oscillation stabilization time is being counted after software STOP mode is released
• When the main clock is stopped
• When the sampling clock is stopped (Ring-OSC)
• When the CPU operates using Ring-OSC
Operation when main clock oscillation is stopped (CLME bit = 1)
If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is gener-
ated as shown in Figure 25-3.
Ring-OSC
Internal
2. The clock monitor is stopped while Ring-OSC is stopped.
clock
Table 25-2: Operation Status of Clock Monitor (When CLM.CLME Bit = 1,
During Ring-OSC Operation) (CKSEL Connected to Ring-OSC)
HALT mode
IDLE mode
STOP mode
Figure 25-3: When Oscillation of Main Clock Is Stopped
Operation
Mode
-
-
User’s Manual U16702EE3V2UD00
Chapter 25 Clock Monitor
Oscillates
Stops
Stops
Stops
Status of Main Clock
Four Ring Oscillation clocks
Oscillates
Oscillates
Stops
Status of Ring-OSC
Clock
Note 1
Note 1
Operates
Stops
Stops
Stops
Status of Clock Moni-
Note 2
tor
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