upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 687

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Remarks: 1. Default Priority: The priority order when two or more maskable interrupt requests occur
Type
Classifica-
tion
2. The execution address of the illegal instruction when an illegal opcode exception occurs
Restored PC:
nextPC:
is calculated by (Restored PC − 4).
Default
Priority
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Chapter 17 Interrupt/Exception Processing Function
INTUA1T
INTAD
INTC0ERR
INTC0WUP
INTC0REC
INTC0TRX
INTC30I
INTC30O
INTC31I
INTC31O
INTTQ1OV
INTTQ1CC0 TMQ1 capture0 trigger input
INTTQ1CC1 TMQ1 capture1 trigger input
INTTQ1CC2 TMQ1 capture2 trigger input
INTTQ1CC3 TMQ1 capture3 trigger input
INTC1ERR
INTC1WUP
INTC1REC
INTC1TRX
INTDMA0
INTDMA1
INTDMA2
INTDMA3
INTDMA4
INTDMA5
Table 17-1: Interrupt/Exception Source List (3/3)
Name
User’s Manual U16702EE3V2UD00
at the same time. The highest priority is 0.
The value of the program counter (PC) saved to EIPC or FEPC when
interrupt processing is started. Note, however, that the restored PC
when a non-maskable or maskable interrupt is acknowledged while
one of the following instructions is being executed does not become
the nextPC (if an interrupt is acknowledged during interrupt execution,
execution stops, and then resumes after the interrupt servicing has
finished).
The PC value that starts the processing following interrupt/exception
processing.
•
•
•
UARTA1 transfer completion
AD conversion completion
AFCAN0 error occurrence
AFCAN0 wake up request
AFCAN0 reception completion
AFCAN0 transfer completion
CSI30 interrupt
CSI30 overflow
CSI31 interrupt
CSI31 overflow
TMQ1 overflow
AFCAN1 error occurrence
AFCAN1 wake up request
AFCAN1 reception completion
AFCAN1 transfer completion
DMA0 transfer completion
DMA1 transfer completion
DMA2 transfer completion
DMA3 transfer completion
DMA4 transfer completion
DMA5 transfer completion
Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W)
Division instructions (DIV, DIVH, DIVU, DIVHU)
PREPARE, DISPOSE instructions (only if an interrupt is gener-
ated before the stack pointer is updated)
Trigger
Generating
UARTA1
AD
AFCAN0
AFCAN0
AFCAN0
AFCAN0
CSI30
CSI30
CSI31
CSI31
TMQ1
TMQ1
TMQ1
TMQ1
TMQ1
AFCAN1
AFCAN1
AFCAN1
AFCAN1
DMA
DMA
DMA
DMA
DMA
DMA
Unit
Exception
02C0H 000002C0H nextPC C0ERRIC
02D0H 000002D0H nextPC C0WUPIC
03D0H 000003D0H nextPC C1ERRIC
02A0H 000002A0H nextPC UA1TIC
02B0H 000002B0H nextPC ADIC
02E0H 000002E0H nextPC C0RECIC
02F0H 000002F0H nextPC C0TRXIC
0300H
0310H
0320H
0330H
0360H
0370H
0380H
0390H
03A0H 000003A0H nextPC TQ1CCIC3
03E0H 000003E0H nextPC C1WUPIC
03F0H 000003F0H nextPC C1RECIC
0400H
0410H
0420H
0430H
0440H
0450H
0460H
Code
00000300H nextPC C30IC
00000310H nextPC C30OC
00000320H nextPC C31IC
00000330H nextPC C31OC
00000360H nextPC TQ1OVIC
00000370H nextPC TQ1CCIC0
00000380H nextPC TQ1CCIC1
00000390H nextPC TQ1CCIC2
00000400H nextPC C1TRXIC
00000410H nextPC DMAIC0
00000420H nextPC DMAIC1
00000430H nextPC DMAIC2
00000440H nextPC DMAIC3
00000450H nextPC DMAIC4
00000460H nextPC DMAIC5
Address
Handler
Restored
PC
Interrupt
Register
Control
687