upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 435

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Note: This register can be rewritten only when the CBnPWR bit = 0. However, the CBnPWR bit can
When the CBnTMS bit = 0, the single transfer mode is set in which continuous transmission/reception is not sup-
ported. Even when only transmission is executed, an interrupt is output on completion of reception transfer.
The CBnSCE bit controls starting of the transfer operation in the master mode.
If only reception is enabled in the single transfer mode (CBnRXE bit = 1, CBnTXE bit = 0), the reception operation
is started when the CBnRX register is read. To read the last receive data, clear the CBnSCE bit to 0, read the last
receive data, and then disable starting the next reception operation.
Similarly, if only reception is enabled in the continuous transfer mode (CBnTMS bit = 1), starting the reception
operation can be disabled after completion of reception of the last receive data, by clearing the CBnSCE bit to 0
one clock before reception of the last receive data is completed. After the last data is read, reception is enabled
by setting the CBnSCE bit to 1 again and reading the CBnRX register. In the slave reception mode, the CBnSCE
bit also enables the internal operating clock, and therefore, set the CBnSCE bit to 1.
CBnTMS
CBnSCE
0
1
0
1
also be set to 1 at the same time as rewriting these bits
Note
Disable transfer operation.
Enable transfer operation.
Single transfer mode
Continuous transfer mode
Figure 13-2: CSIBn Control Register 0 (CBnCTL0) Format (2/2)
Chapter 13 3-Wire Serial Interface (CSIB)
User’s Manual U16702EE3V2UD00
Specification of start transfer disable or enable
Specification of transfer mode
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