upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 481

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

14.3.7 Description of the Single Buffer Transfer Mode
Transfer start condition in single buffer transfer mode:
A transfer starts once the transmission data (pointed to by the SIO Loading FIFO pointer) is transferred
from the FIFO buffer to the serial shift register SIO. At that time, the transfer status flag CSOT turns to
“1”. The CS3n[3:0] pins output the chip select data from the FIFO buffer.
At the end of the transfer:
(A) If SIRB is empty, the received data is stored from SIO to SIRB, and transfer end interrupt signal
(B) If SIRB is not empty, the storing of receive data, INTC3nI generation and SIO Loading FIFO
(C) In transmit only mode, if transmission data is available in the FIFO buffer, the next transfer will start
[CTXE = 1 or CRXE = 1] and
[Data exists in FIFO (SFEMP = 0)]
INTC3nI is generated (in transmit only mode, INTC3nI will be generated only when the FIFO buffer
becomes empty). Finally, the SIO L7oading FIFO pointer is incremented.
pointer incrementing wait for the SIRB to be emptied by a software read operation.
immediately, regardless of the SIRB buffer condition.
CS3n3 to CS3n0 pins
SFCS register
3, 2, 1, 0
19
CS
3, 2, 1, 0
CS data 5
CS data 4
CS data 3
CS data 2
CS data 1
CS data 0
Figure 14-17: Single Buffer Transfer Mode Data Handling
SFCS
16 15
SO3n pin
Chapter 14 Queued CSI (CSI30, CSI31)
Data
15, 14, 13, ......
User’s Manual U16702EE3V2UD00
15, 14, 13, ......2, 1, 0
Transmission data 4
Transmission data 3
Transmission data 2
Transmission data 1
Transmission data 0
SFDB register
SFDB
2, 1, 0
SIRB
SIO
SIRBE
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SFA register
SI3n pin
3, 2, 1, 0
SFP
Diff
Writing FIFO
pointer
SIO Loading
FIFO pointer
INC
INC
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