upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 278

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

7.5.3 External event counter mode (TPnMD2 to TPnMD0 = 001)
In the external event count mode, the external event count input (TIPn0 pin input) is used as a count-up
signal. Regardless of the setting of the TPnEEE bit of the TPnCTL0 register, 16-bit timer/event counter
P counts up the external event count input (TIPn0 pin input) when it is set in the external event count
mode. In the external event count mode, an interrupt request (INTTPnCC0) is generated when the set
value of the TPnCCR0 register matches the value of the 16-bit counter, and the value of the 16-bit
counter is cleared.
When a value is set to the TPnCCR0 register with a write instruction from the CPU, it is transferred to
the CCR0 buffer register through any time write, and is compared with the 16-bit counter value.
In the external event counter mode, the 16-bit counter is cleared only upon a match between the value
of the 16-bit counter and the value of the CCR0 buffer register.
The 16-bit counter can not be cleared using TPnCCR1 register. However, the setting value of the
TPnCCR1 register is transferred to the CCR1 buffer register and compared with the value of the 16-bit
counter, and an interrupt request (INTTPnCC1) is output if these values match.
Moreover, TOPnm pin output is also possible by setting the TPnOEm bit to 1.
When performing timer output with the TOPn1 pin, set the same values to TPnCCR0 register and
TPnCCR1 register since the 16-bit counter cannot be cleared with CCR1 buffer register.
The TPnCCR0 register can be rewritten when TPnCE = 1. When TPnCCR1 register is not used, it is
recommended to set TPnCCR1 register to FFFFH.
Notes: 1. Selection of the TPnEEE bit has no influence.
Remark:
278
2. The 16-bit counter is not cleared upon a match between the 16-bit counter and the CCR1
Figure 7-19: Flowchart of Basic Operation in External Event Counter Mode
buffer register.
n = 0 to 3
m = 0, 1
• Set external event count mode (TPnCTL0:
• Set valid edge (TPnIOC2: TPnEES1,
• Set compare register (TPnCCR0,
TPnMD2 to TPnMD0 = 001)
TPnEES0)
TPnCCR1)
→ Transfer values of TPnCCR0 and
Enable timer operation (TPnCE = 1)
TPnCCR1 to CCR0 buffer register
Clear and start 16-bit counter
Chapter 7 16-Bit Timer/Event Counter P
CCR1 buffer register
and CCR1 buffer register
16-bit counter matches
16-bit counter matches
CCR0 buffer register.
Initial setting
User’s Manual U16702EE3V2UD00
START
Note 1
Note 2
INTTPnCC1 occurs
INTTPnCC0 occurs