upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 222

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

5.6 Idle State Insertion Function
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in
the bus cycle that is executed for each space selected by the chip select function in the multiplexed
address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state.
By inserting an idle state, the data output float delay time of the memory can be secured during read
access (an idle state cannot be inserted during write access).
Whether the idle state is to be inserted can be programmed by using the bus cycle control register
(BCC).
An idle state is inserted for all the areas immediately after system reset.
(1)
Cautions: 1. The internal ROM, internal RAM, and internal peripheral I/O areas are not subject
Caution:
222
Symbol
BCC
R/W
CSn
Bus cycle control register (BCC)
This register can be read or written in 16-bit units.
signal
2. Write to the BCC register after reset, and then do not change the set values. Also,
Be sure to set bits 15, 13, 11, 9, 7, and 5 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0
to 0.
15
1
7
1
BCn1
to idle state insertion.
do not access an external memory area other than the one for this initialization
routine until the initial settings of the BCC register are complete. However,
external memory areas whose initial settings are complete may be accessed.
0
1
14
0
6
0
Figure 5-7: Bus Cycle Control Register (BCC) Format
Not inserted
Inserted
13
1
5
1
Chapter 5 Bus Control Function
User’s Manual U16702EE3V2UD00
Specifies insertion of idle state (n = 0, 1)
12
0
4
0
BC11
I___I
CS1
11
1
3
10
0
2
0
BC01
I___I
CS0
9
1
1
8
0
0
0
FFFFF48AH
Address
After reset
AAAAH