upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 415

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

12.4 Interrupt Request Signals
UARTAn generates the following two types of interrupt request signals.
Of these two interrupt request signals, the reception complete interrupt request signal has the higher
priority by default, and the priority of the transmission enable interrupt request signal is lower.
(1)
(2)
• Reception complete interrupt request signal (INTUAnR)
• Transmission enable interrupt request signal (INTUAnT)
Reception complete interrupt request signal (INTUAnR)
When data is shifted in to the receive shift register with reception enabled, and transferred to the
UAnRX register, the reception complete interrupt request signal is generated.
This interrupt request signal can also be generated if a reception error occurs, instead of a recep-
tion error interrupt.
When the reception complete interrupt request signal is acknowledged and the data is read, read
the UAnSTR register to check that the result of reception is not an error.
Reception complete interrupt request signals are not generated while reception is disabled.
Transmission enable interrupt request signal (INTUAnT)
The transmission enable interrupt request signal is generated when transmit data is transferred
from the UAnTX register to the UARTAn transmit shift register with transmission enabled.
Chapter 12 Asynchronous Serial Interface A (UARTA)
Table 12-3: Interrupts and Their Default Priority
Transmission enable
Reception complete
User’s Manual U16702EE3V2UD00
Interrupt
Priority
High
Low
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