upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 691

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upd70f3402

Manufacturer Part Number
upd70f3402
Description
32-/16-bit Single-chip Microcontroller With Can Interface
Manufacturer
Renesas Electronics Corporation.
Datasheet
17.2.2 Restore
(1)
Caution:
Remark:
(2)
From NMI
Execution is restored from the NMI by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers
control to the address of the restored PC.
<1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the EP bit of
<2> Transfers control back to the address of the restored PC and PSW.
Figure 17-3 illustrates how the RETI instruction is processed.
From INTWDT2
Execution cannot be returned from INTWDT by the RETI instruction. Execute a system reset after
the interrupt has been serviced.
the PSW is 0 and the NP bit of the PSW is 1.
When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during
non-maskable interrupt servicing, in order to restore the PC and PSW correctly dur-
ing recovery by the RETI instruction, it is necessary to set PSW.EP back to 0 and
PSW.NP back to 1 using the LDSR instruction immediately before the RETI instruc-
tion.
The solid line shows the CPU processing flow.
1
Chapter 17 Interrupt/Exception Processing Function
Original processing restored
PC
PSW
Figure 17-3: RETI Instruction Processing
RETI instruction
User’s Manual U16702EE3V2UD00
PSW.EP
PSW.NP
0
0
EIPC
EIPSW
1
PC
PSW
FEPC
FEPSW
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