upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 516

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Caution:
Remarks: 1. This bit is a trigger bit only. When reading the bit, the read value is always 0.
Caution:
Remark:
516
FCLR
STG
EN
0
1
0
1
0
1
Write to FCLR = 1 is permitted only when EN = 0 (DMCHCn register).
2. The RQST flag is cleared two clock cycles after setting FCLR = 1.
Do not set FCLR and STG bits at the same time. If set at the same time, FCLR gets
priority.
This bit is a trigger bit only. When reading the bit, the read value is always 0.
DMA transfer is disabled or the total number of DMA transfers is finished.
If EN set to 0 while a “Single” or “Fixed Channel” transfer is active, the DMA transfer is stopped
(the DMA source address, destination address, and transfer count registers are held.). When EN
is set to 1 again, the DMA transfer is re-started.
DMA transfer is enabled and/or the total number of DMA transfers is not finished.
No change
Clear any pending DMA transfer request.
No change
Generate a DMA transfer trigger.
Figure 15-10: DMA Channel Control Register (DMCHCn) Format (4/4)
Chapter 15 DMA Functions (DMA Controller)
User’s Manual U16702EE3V2UD00
DMA Request Clear Trigger
DMA Software Trigger
DMA Transfer Enable