upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 66

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

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Bit position
FEPSW
31 to 16
15 to 0
FEPC
ECR
NMI status saving registers (FEPC and FEPSW)
FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.
If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the
program status word (PSW) are saved to FEPSW.
The address of the instruction next to the one of the instruction under execution, except some
instructions, is saved to FEPC when an NMI occurs.
The current contents of the PSW are saved to FEPSW.
Because only one set of NMI status saving registers is available, the contents of these registers
must be saved by program when multiple interrupts are enabled.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these
bits are always fixed to 0).
Interrupt source register (ECR)
The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or
interrupt occurs. This register holds the exception code of each interrupt source. Because this reg-
ister is a read-only register, data cannot be written to this register using the LDSR instruction.
The list of exception codes is tabulated in Table 17-1, “Interrupt/Exception Source List,” on
page 685.
31
31
31
0
0
Figure 3-4: NMI Status Saving Registers (FEPC and FEPSW) Format
Bit name
0
0
FECC
EICC
0 0 0 0
0 0 0 0
Figure 3-5: Interrupt Source Register (ECR) Format
26 25
Exception code of non-maskable interrupt (NMI)
Exception code of exception or maskable interrupt
0
FECC
0
0 0 0 0
User’s Manual U16702EE3V2UD00
Chapter 3 CPU Function
0
0
0 0 0 0
16 15
(PC contents)
0
0
0 0 0 0
Meaning
EICC
8
(PSW contents)
0
0
0
(x: Undefined)
(x: Undefined)
00000000H
After reset
000000xxH
0xxxxxxxH
After reset
After reset